• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1271-1282
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• 2005

Recently, PC-based control is incredibly developed in the industrial control field, but it is difficult for PLC programming in PC. Therefore, I need to develop the softeware PLC, which support the international PLC programming standard(IECl131-3) and can be applied to diverse control system by using C language. In this paper, I have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user which is used over $90\%$ among the 5 PLC languages, is converted to IL, which is one of intermediate codes, and IL is converted to the standard C rode which can be used in a commercial editor such as Visual C++. In ISPLC, the detection of logical error in high level programming(C) is more eaier than PLC programming itself The study of code conversion of LD->IL->C is firstly tried in the world as well as KOREA. I developed an execution engine with a good practical application. To show the effectiveness of the developed system, 1 applied it to a practical case, a real time traffic control(RT-TC) system. ISPLC is minimized the error debugging and programming time owing to be supported by windows application program.

• Journal of Construction Engineering and Project Management
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• v.8 no.4
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• pp.1-24
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• 2018

In the last decade, the use of Building Information Modeling (BIM) as a new technology has been applied with traditional Computer-aided design implementations in an increasing number of architecture, engineering, and construction projects and applications. Its employment alongside construction management, can be a valuable tool in helping move these activities and projects forward in a more efficient and time-effective manner. The traditional stakeholders, i.e., Owner, A/E and the Contractor are involved in this BIM system that is used in almost every activity of construction projects, such as design, cost estimate and scheduling. This article extracts major features of the application of BIM from perspective of participating BIM components, along with the different phrases, and applies to them a logistic analysis using a fuzzy performance tree, quantifying these phrases to judge the effectiveness of the BIM techniques employed. That is to say, these fuzzy performance trees with fuzzy logic concepts can properly translate the linguistic rating into numeric expressions, and are thus employed in evaluating the influence of BIM applications as a mathematical process. The rotational fuzzy models are used to represent the membership functions of the performance values and their corresponding weights. Illustrations of the use of this fuzzy BIM performance tree are presented in the study for the uninitiated users. The results of these processes are an evaluation of BIM project performance as highly positive. The quantification of the performance ratings for the individual factors is a significant contributor to this assessment, capable of parsing vernacular language into numerical data for a more accurate and precise use in performance analysis. It is hoped that fuzzy performance trees and fuzzy set analysis can be used as a tool for the quality and risk analysis for other construction techniques in the future. Baldwin's rotational models are used to represent the membership functions of the fuzzy sets. Three scenarios are presented using fuzzy MEAN, AND and OR gates from the lowest to intermediate levels of the tree, and fuzzy SUM gate to relate the intermediate level to the top component of the tree, i.e., BIM application final performance. The use of fuzzy MEAN for lower levels and fuzzy SUM gates to reach the top level suggests the most realistic and accurate results. The methodology (fuzzy performance tree) described in this paper is appropriate to implement in today's construction industry when limited objective data is presented and it is heavily relied on experts' subjective judgment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.38-43
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• 2006

In this paper, we propose the efficient dead pixel detection algorithm for CMOS image sensors and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However, the presence of the dead pixels degrade the image quality. To detect the dead pixels, the proposed algorithm is composed of scan, trace and detection step. The experimental results showed that it could detect 99.99% of dead pixels. It was designed in a hardware description language and total logic gate count is 3.2k using 0.25 CMOS standard cell library.

• Journal of Computing Science and Engineering
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• v.3 no.2
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• pp.127-141
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• 2009

In this paper, we describe our vision of a "Just-in-time" initiative to solve the Data Interoperability Problem (a.k.a. INTEROP.) We provide an architectural overview of our initiative which draws upon existing technologies to develop an immersive and collaborative approach which aims at empowering data stakeholders (e.g., data producers and data consumers) with integrated tools to interact and collaborate with each other while directly manipulating visual representations of their data in an immersive environment (e.g., implemented via Second Life.) The semantics of these visual representations and the operations associated with the data are supported by ontologies defined using the Common Logic Framework (CL). Data operations gestured by the stakeholders, through their avatars, are translated to a variety of generated resources such as multi-language source code, visualizations, web pages, and web services. The generality of the approach is supported by a plug-in architecture which allows expert users to customize tasks such as data admission, data manipulation in the immersive world, and automatic generation of resources. This approach is designed with a mindset aimed at enabling stakeholders from diverse domains to exchange data and generate new knowledge.

• Journal of KIISE:Software and Applications
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• v.35 no.9
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• pp.529-537
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• 2008

Since concurrent software is hard to debug, the verification of such systems inevitably needs automatic tools which support exhaustive searching. Bounded Model Checking (BMC) is one of them. Within a bound k, BMC exhaustively check some errors in execution traces of the given system. In this paper, we introduce the tool that performs BMC for LTS, modeling language for concurrent programs. In this tool, a property is described by a FLTL formula, which is suitable to present the property with actions in a LTS model. To experiment with existential model checkers and out tool, we compare and analysis the performance of the developed tool and others.

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.421-426
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• 2006

Because the 3-Tier structure cia share a business logic, the reuse of existing code could be guaranteed Al so tiny and little client application in charge of user interface can he made that it doesn't need plenty of client memory and calculation capability. Catering system that capable of meal material code management autom atic production of requiring quantity, purchase and shipping management menu management, account management was developed for grafting 3-Tire structure technology using database language and ADO(ActiveX Dat a Object). This system improved production in field of school lunch program and saved o(poises. finally, this system is suitable to the service environment of school lunch program and lots of utilizations would be anticipated.

• Proceedings of the KOSOMBE Conference
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• v.1990 no.11
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• pp.11-14
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• 1990

The detection of pulmonary blood vessels is very difficult owing to their complex tree structures and different widths. In this paper, We propose a new detection algorithm. The motivation of this algorithm is that Han is the best detector. So, this algorithm is developed to imitate the human searching process. To realize it, the algorithm consist of two components. One is Pyramid Images whose one pixel is median value of four pixels of the previous low level. Searching gradually from high level to low level, We concentrate on global and main information of structure at the first. Then based on it, We search the detailed data in low level. The other is fuzzy logic which makes it easy to convert searching process expressed as human language into numeric multi_value. This algorithm showes speedy and robust results. But the more study on both human searching process and the detection of small part is needed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.51-57
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• 1980

Any switching function can be constructed with universal building block of MAND gate. Threelevel AND-NOT logic networks with only true inputs are called TANT networks. Systematic approach to TANT minimization starts from the UF type minterm with the smallest subscript and ends when UF type minterms are all covered. Optinal PEI is composed of CPPI or EPPi without C-C table. The algorithm in this work is usful in solving TANT optimization porblem of four or five variables by hand solution. When variable are six or more, it is required to be solved by computer, A CAD software package of this algorithm with FORTRAN IV language is made to solve such problems.