• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.5
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• pp.1396-1412
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• 2023

Conversation modeling is an important and challenging task in the field of natural language processing because it is a key component promoting the development of automated humanmachine conversation. Most recent research concerning conversation modeling focuses only on the current utterance (considered as the current question) to generate a response, and thus fails to capture the conversation's logic from its beginning. Some studies concatenate the current question with previous conversation sentences and use it as input for response generation. Another approach is to use an encoder to store all previous utterances. Each time a new question is encountered, the encoder is updated and used to generate the response. Our approach in this paper differs from previous studies in that we explicitly separate the encoding of the question from the encoding of its context. This results in different encoding models for the question and the context, capturing the specificity of each. In this way, we have access to the entire context when generating the response. To this end, we propose a deep neural network-based model, called the Context Model, to encode previous utterances' information and combine it with the current question. This approach satisfies the need for context information while keeping the different roles of the current question and its context separate while generating a response. We investigate two approaches for representing the context: Long short-term memory and Convolutional neural network. Experiments show that our Context Model outperforms a baseline model on both ConvAI2 Dataset and a collected dataset of conversational English.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.2
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• pp.160-166
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• 2007

When a mail was given to users, each user's response could be different according to his or her preference. This paper presents a solution for this situation by constructing a user preferred ontology for anti-spam systems. To define an ontology for describing user behaviors, we applied associative classification mining to study preference information of users and their responses to emails. Generated classification rules can be represented in a formal ontology language. A user preferred ontology can explain why mail is decided to be spam or ron-spam in a meaningful way. We also suggest a new rule optimization procedure inspired from logic synthesis to improve comprehensibility and exclude redundant rules.

• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.44-50
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• 2003

A security system consisted of an infrared sensor and PLD(Programmable Logic Device) was fabricated to prevent an intruder. The fabricated system detect the intruder using infrared sensor and has password key pad to permit someone to enter the house and office. The control circuit of the system is designed by VHDL(Very high speed integrated Hardware Description Language). The system was demonstrated in various conditions and the output signals were displayed in LCD, LED, buzzer and so on. This designed system in this paper has a advantage to supplement additional function with ease.

• Journal of Welding and Joining
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• v.10 no.4
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• pp.199-212
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• 1992

Expert system is a practical application part of the artificial intelligence and can be generally described as a computer-based system designed to simulate the knowledge and reasoning of a human expert, and to make that knowledge conveniently available to other people in a useful way. Expert systems consist of three major components, knowledge base, inference engine and user interface. In this paper, it is aimed to construct a prototype system to design the horizontal-typed pressure vessel. To do this, a representative artificial programming language, Turbo Prolog, was employed, and the knowledge representation was mainly done by the production rule such as "If(condition), than (action)" style and by the predicate logic. In the developed system, it was quite easy to represent the knowledge of "If(condition), then (action)"style and by the predicate logic. In the developed system, it was quite easy to represent the knowledge of "If(condition). then(action)" style and the various table-like data. It was also effective to represent the graphics. Though this expert system is by now small and incomplete, it is possible to expand it to a larger and refined system later.rger and refined system later.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.284-287
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• 2001

In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.173-183
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• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.408-411
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• 2006

유비쿼터스 컴퓨팅 환경에서 서비스를 제공함에 있어 지능적인 수행 능력은 사용자의 만족도를 높여주는 핵심 요소이다. 시스템의 지능을 부여하기 위해서는 지식을 관리, 처리, 활용하는 기능이 필요한데, 이들 기능은 그 지식이 어떻게 표현되어 있는지에 큰 영향을 받는다. 일차 술어 논리 기반 지식 표현 방법은 폭넓은 표현 범위와 유연한 지식 정의, 추론 방법으로 선호되고 있지만, 복잡한 계산 비용을 갖고 있기 때문에, 전문적인 지식 처리 시스템이 아닌 경우, 불필요한 계산 비용이 소요된다. Description Logic은 Frame기반 지식 표현 방식으로 일차 술어 논리를 사용하는 것보다 지식을 표현할 수 있는 범위는 제한적이지만, 빠른 추론 결과를 보장해 준다. 유비쿼터스 컴퓨팅 환경에서는 분산된 다양한 오브젝트들이 협력과정을 통해 사용자에게 지능적인 서비스를 제공하게 되고, 이들 개별적인 오브젝트들은 저사양의 계산능력을 갖고 있다고 가정된다. 그러므로, 저사양의 컴퓨팅 오브젝트들을 조합하여 지능적인 서비스를 성공적으로 제공하기 위해서, 각각의 오브젝트들은 제한된 지식을 효과적으로 관리할 수 있는 방법이 필요하다. 이를 위해 본 논문에서는 Frame 기반의 Description Logic을 기반으로 SUNHI의 표현 범위를 가진 인식론적 온톨로지 표현 언어를 제안하고, SUNHI의 표현 범위의 효율성을 증명하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1579-1587
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• 2010

In this paper, we design the PCS(Physical Coding Sublayer) transmitting and receiving module for 400/1000 Ethernet and verify the performance of it through logic simulation. In this work, we defined each function module and internal/external control signals and implemented them using HDL programming language. We also designed 64B/66B encoding/decoding, scrambling/descrambling including operation mode, detection of invalid frames, and multi-lane based distribution/arrangement. It was simulated using ModelSim and verified in terms of the operation and timing according to input data. The simulation result shows that all designed modules in 400/100G Ethernet are correctly performed.

• Korean Journal of Logic
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• v.18 no.3
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• pp.337-358
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• 2015

Vann Mcgee produced "counterexamples" to Modus Ponens in "A Counterexample to Modus Ponens". Discussions about the examples tended to focus on a probabilistic reading of conditional statements. This article attempts to establish both (1) Modus Ponens is a deductively valid rule of inference, and (2) the counterexample-like appearance of Mcgee's example can be (and should be) explained without making a reference to the notion of conditional probability. The reason why his examples seem to counter Modus Ponens is found rather within the ambiguity a conditional statement exhibits. That is, Mcgee's examples are cases of equivocation on the conditional statements involved.