• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.382-383
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• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.535-538
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• 2005

We report the influence of the threshold voltage and mobility fluctuation in TFT on current mode digital circuit performance. We found that the threshold voltage showed more serious circuit malfunction. We studied new circuit configuration for improvement.

• Proceedings of the Korean Magnestics Society Conference
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• 2017.05a
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• pp.46-47
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• 2017

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.114-114
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• 2012

Even though graphene was introduced with a great hope to replace silicon in future, small (or zero) band gap and poor stability have become major challenges in graphene electronics. Especially, rectification and amplification function which are the elemental functions of silicon device, is very difficult to implement without a bandgap. However, the graphene can still be used in many other device applications if the merits of graphene are creatively utilized. For example, graphene can be applied to almost any kind of substrate. Its conductivity can be varied in some degree using electric field, charge dipole, attached molecules, and many other ways. Recently, graphene stacked with ferroelectric materials or piezoelectric materials has been actively studied for various device applications. In this talk, various device applications of graphene using hybrid stack or novel device structure will be introduced and their prospect will be discussed.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.379-387
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• 2015

A custom power device provides an integrated solution to the present problems that are faced by the utilities and power distribution. In this paper, a new controller is designed which is connected to a multiconverter unified power quality conditioner (MC-UPQC) for improving the power quality issues adopted modified synchronous reference frame (MSRF) theory with Fuzzy logic control (FLC) technique. This newly designed controller is connected to a source in order to compensate voltage and current in two feeders. The expanded concept of UPQC is multi converter-UPQC; this system has a two-series voltage source inverter and one shunt voltage source inverter connected back to back. This configuration will helps mitigate any type of voltage / current fluctuations and power factor correction in power distribution network to improve power quality issues. In the proposed system the power can be conveyed from one feeder to another in order to mitigate the voltage sag, swell, interruption and transient response of the system. The control strategies of multi converter- UPQC are designed based on the modified synchronous reference frame theory with fuzzy logic controller. The fast dynamics response of dc link capacitor is achieved with the help of Fuzzy logic controller. Different types of fault conditions are taken and simulated for the analysis and the results are compared with the conventional method. The relevant simulation and compensation performance analysis of the proposed multi converter-UPQC with fuzzy logic controller is performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.616-619
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• 2003

In this paper, we develop an input device equipped with accelerometers and gyroscopes. The installed sensors measure the inertial measurements i.e., accelerations and angular rates produced by the movement of the system when a user is writing on the plane surface or in the three dimensional space. The gyroscope measurement are integrated once to give the attitude of the system and consequently used to remove the gravity included in the acceleration measurements. The compensated accelerations bin doubly integrated to yield the position of the system. Due to the integration processes involved in recovering the users'motions, the accuracy of the position estimation significantly deteriorates with time. Among various error sources of the system incorrect estimation of attitude causes the largest portion of the positioning error since the gravity is not fully cancelled. In order to solve this problem, we propose a Kalman filler-based attitude estimation algorithm which fuses measurement data from accelerometers and gyroscopes by fuzzy logic approach. In addition, the online calibration of the gyroscope biases are performed in parallel with the attitude estimation to give more accurate attitude estimation. The effectiveness and the feasibility of the presented system is demonstrated through computer simulations and actual experiments.