• Journal of the Korean Data and Information Science Society
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• v.21 no.6
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• pp.1125-1136
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• 2010

Lately there exist increasing demands for online abnormality monitoring over trajectory stream, which are obtained from moving object tracking devices. This problem is challenging due to the requirement of high speed data processing within limited space cost. In this paper, we present a FADA (Fuzzy Anomaly Detection Algorithm) which constructs normal profile by computing mobility feature information from the GPS (Global Positioning System) logs of mobile devices in MANETs (Mobile Ad-hoc Networks), computes a fuzzy dissimilarity between the current mobility feature information of the mobile device and the mobility feature information in the normal profile, and detects effectively the anomaly behaviors of mobile devices on the basis of the computed fuzzy dissimilarity. The performance of proposed FADA is evaluated through simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Journal of Power Electronics
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• v.6 no.3
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• pp.235-244
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• 2006

Recently, speed sensorless vector control for synchronous reluctance motors (SYRMs) has deserved attention because of its advantages. Although rotor angle calculation using flux estimation is a straightforward approach, the DC offset can cause an increasing pure integrator error in this estimator. In addition, this method is affected by parameter fluctuation. In this paper, to control the motor at the low speed region, a modified programmable cascaded low pass filter (MPCPLF) with sensorless online parameter identification based on a block pulse function is proposed. The use of the MPCLPF is suggested because in programmable, cascade low pass filters (PCLPF), which previously have been applied to induction motors, the drift increases vastly wl)en motor speed decreases. Parameter identification is also used because it does not depend on estimation accuracy and can solve parameter fluctuation effects. Thus, sensorless speed control in the low speed region is possible. The experimental system includes a PC-based control with real time Linux and an ALTERA Complex Programmable Logic Device (CPLD), to acquire data from sensors and to send commands to the system. The experimental results show the proposed method performs well, speed and angle estimation are correct. Also, parameter identification and sensorless vector control are achieved at low speed, as well as, as at high speed.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2705-2707
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• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level. Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means of the decision of the operating system. In this paper, we designed of low power system by using power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.63-69
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• 2014

RFIDs have not become widespread as expected partly due to the cost, size, read range, and reliability problems of tags. The success rate of reading must be improved in order for RFIDs to be widely adopted. Quality control of tags is crucial to meet this requirement. In this study, we designed and implemented a high-performance reader used in inspection equipment that conducts prior inspection of tags. To improve performance of the developed reader, the baseband modem and command processor (CP) were designed using H/W logic and implemented with FPGA. The inspection of small pitch inlays was made possible through the antenna shielding device and H/W command processor function. This equipment enables accurate evaluation of performance and identification of tags satisfying a given read range. By contributing to sort out defective tags, the results can ultimately lead to more stable RFID services.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1480-1483
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• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.131-137
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, the principle of digital to radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Journal of Korea Multimedia Society
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• v.19 no.8
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• pp.1445-1452
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• 2016

Recently Mobile Software Applications are developed in various languages and stored in App Store. App Users selectively use appropriate apps for the owned hardware. In other words, it depends on the kinds of operating systems of the apps whether to use or not to use the applications in various languages. The apps should be differently implemented according to the kind of the user's device, though they provide the same functions. To solve these problems, it is necessary to define an independent function specification method which is not dependent to a specific system environment. In this paper, the Mobile Application Developing Framework is suggested, which incorporates all of the development process. Standardized models are proposed which can be used in the analysis and design steps. In implementation phase, a technique for cross framework design is suggested so as to implement a platform dependent mobile app.

• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• Journal of Sensor Science and Technology
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• v.31 no.5
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• pp.324-329
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• 2022

This paper proposes a shift-register-based multichannel ultrasonic focusing delay control method using a complex programmable logic device (CPLD) for a high resolution of ultrasonic focusing system. The proposed method can achieve the ultrasonic focusing through the delay control of driving signals of each ultrasonic transducer of an ultrasonic array. The delay of the driving signals of all ultrasonic channels can be controlled by setting the shift register in the CPLD. The experiment verified that the frequency of the clock used for the delay control increased, the error of the focusing point decreased, and the diameter of the focusing point decreased as the length of the shift register in the proposed method. The proposed method used only one CPLD for ultrasonic focusing and did not require to use complex hardware circuits. Therefore, the resources required for the design of an ultrasonic focusing system could be reduced. The proposed method can be applied to the fields of human computer interaction (HCI), virtual reality (VR) and augmented reality (AR).