• Journal of IKEEE
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• v.14 no.2
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• pp.64-68
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• 2010

This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2576-2578
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• 2001

Elliptic curve cryptosystems based on discrete logarithm problem in the group of points of an elliptic curve defined over a finite field. The discrete logarithm in an elliptic curve group appears to be more difficult than discrete logarithm problem in other groups while using the relatively small key size. An implementation of elliptic curve cryptosystems needs finite field arithmetic computation. Hence finite field arithmetic modules must require less hardware resources to archive high performance computation. In this paper, a new architecture of finite field multiplier using conversion scheme of normal basis representation into polynomial basis representation is discussed. Proposed architecture provides less resources and lower complexity than conventional bit serial multiplier using normal basis representation. This architecture has synthesized using synopsys FPGA express successfully.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

• Journal for History of Mathematics
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• v.27 no.6
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• pp.409-419
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• 2014

In school mathematics, the logarithmic function is defined as the inverse function of an exponential function. And the natural logarithm is defined by the integral of the fractional function 1/x. But historically, Napier had already used the concept of logarithm in 1614 before the use of exponential function or integral. The calculation of the logarithm was a hard work. So mathematicians with arithmetic ability made the tables of values of logarithms and people used the tables for the estimation of data. In this paper, we first take a look at the mathematicians and mathematical principles related to the appearance and the developments of the logarithmic tables. And then we deal with the confusions between mathematicians, raised by the estimation data which were known as proportional parts or mean differences in common logarithmic tables.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.3
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• pp.3-12
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• 1999

The public key crytptosystem is represented by RSA based on the difficulty of integer factorization and ElGamal cryptosystem based on the intractability of the discrete logarithm problem in a cyclic group G. The index-calculus algorithm for discrete logarithms in GF${$q^n$}^+$ requires an polynomial factorization. The Niederreiter recently developed deterministic facorization algorithm for polynomial over GF$q^n$ In this paper we implemented the arithmetic of finite field with c-language and gibe an implementation of the Niederreiter's algorithm over GF$2^n$ using normal bases.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.809-811
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• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.581-583
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• 2017

Elliptic curve cyptography is relatively a current cryptography based on point arithmetic on elliptic curves and the Elliptic Curve Discrete Logarithm Problem (ECDLP). This discrete logarithm problems enables perfect forward secrecy which helps to easily generate key and almost impossible to revert the generation which is a great feature for privacy and protection. In this paper, we provide a lightweight Elliptic Curve Diffie-Hellman (ECDH) Key exchange generator that creates a 163 bit long shared key that can be used in an Elliptic Curve Integrated Encryption Scheme (ECIES) as well as for key agreement. The algorithm uses a fast multiplication algorithm that is small in size and also implements the extended euclidean algorithm. This proposed architecture was designed using verilog HDL, synthesized with the vivado ISE 2016.3 and was implemented on the virtex-7 FPGA board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3702-3707
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• 2009

In this paper, a new approximated MAP algorithm for soft bit decision from QAM symbols is proposed for Gray Coded QAM signals, based on the Max-Log-MAP and a Gray coded QAM signal can be separated into independent two Gray coded PAM signal, M-PAM on I axis with M symbols and N-PAM on Q axis with N symbols. The Max-Log-MAP used distance comparisons between symbols to get the soft bit decision instead of mathematical exponential or logarithm functions. But in accordance with the increase of the number of symbols, the number of comparisons also increase with high complexity. The proposed algorithm is used with the Euclidean distance and constituted with plain arithmetic functions, thus we can know intuitively that the algorithm has low implementing complexity comparing to conventional ones.