• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.526-533
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• 2006

In this paper, we presented the synchronization module between RF shower system and RFID Reader to extend interrogating range on Mobile RFID system, Costas Loop and FPLL(Frequency/phase Lock Loop) were used. We achieved compromised range of 3MHz locking frequency, 1ms locking time and figured out remarkable Hopping frequency of the Reader. The prototype of the new designed RFID system has been tested with ISO18000-6 type-B Tag. The read range between designed RFID Reader and Tag has been measured, it increased triple times by adjusting the Shower system output level.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.3
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• pp.200-205
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• 2015

An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

• Journal of Yeungnam Medical Science
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• v.6 no.2
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• pp.217-222
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• 1989

In this study, high frequency oscillatory ventilator was designed and constructed. Using designed by phase-lock loop system, in order to accurately and easily treat both the outlet volume and rpm. A system has been designed and is being evaluated using CD4046A PLL IC. We use this PLL IC for the purpose of motor controls. The device consists of PLL system, pumping mechanism, piston, cylinder, and special crank shaft are required. This system characteristics were as follows : 1) Frequency : 20-1800rpm. 2) Outlet air volume : 1-50cc.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.298-305
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• 2006

The flow around a circular cylinder which oscillates rotationally with a relatively high forcing frequency has been investigated experimentally using flow visualization and hot-wire measurements. Dominant parameters are Reynolds number (Re), oscillation amplitude $({\theta}_A)$, and frequency ratio $F_R=f_f/f_n$, where $f_f$ is the forcing frequency and $f_n$ is the natural frequency of vortex shedding. Experiments were carried out under the conditions of $Re=4.14{\times}10^3,\;{\theta}_A={\pi}/6$, and $0{\leq}F_R{\leq}2$. The effect of frequency ratio $F_R$ on the flow structure of wake was evaluated by measuring wake velocity profile and spectral analysis of hot-wire signal. Depending on the frequency ratio $F_R$, the cylinder wake has 5 different flow regimes. The vortex formation length and vortex shedding frequency are changed significantly before and after the lock-on regime. The drag coefficient was reduced under the condition of $F_R<1.0$ and the maximum drag reduction is about 33% at $F_R=0.8$. However, the drag is increased as $F_R$ increases beyond $F_R=1.0$. This active flow control method can be effective in aerodynamic applications, if the forcing parameters are selected optimally.

• Wind and Structures
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• v.23 no.2
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• pp.143-155
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• 2016

The interaction between two different shaped structures is very important to be understood. Fluid-structure interactions and aerodynamics of a circular cylinder in the wake of a V-shaped cylinder are examined experimentally, including forces, shedding frequencies, lock-in process, etc., with the V-shaped cylinder width d varying from d/D = 0.6 to 2, where D is the circular cylinder diameter. While the streamwise separation between the circular cylinder and V-shaped cylinder was 10D fixed, the transverse distance T between them was varied from T/D = 0 to 1.5. While fluid force and shedding frequency of the circular cylinder were measured using a load cell installed in the circular cylinder, measurement of shedding frequency of the V-shaped cylinder was done by a hotwire. The major findings are: (i) a larger d begets a larger velocity deficit in the wake; (ii) with increase in d/D, the lock-in between the shedding from the two cylinders is centered at d/D = 1.1, occurring at $d/D{\approx}0.95-1.35$ depending on T/D; (iii) at a given T/D, when d/D is increased, the fluctuating lift grows and reaches a maximum before decaying; the d/D corresponding to the maximum fluctuating lift is dependent on T/D, and the relationship between them is linear, expressed as $d/D=1.2+{\frac{1}{e}}T/D$; that is, a larger d/D corresponds to a greater T/D for the maximum fluctuating lift.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.188-191
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• 2005

A common feature in various methods of optical interferometry for absolute distance measurements is the use of multiple monochromatic light components either in sequence or in parallel at the same time. Two or multiple wavelength synthesis has been studied though its performance is vulnerable to the frequency instability of the light source. Recently continuous frequency modulation is considered a promising method with availability of wide band tunable diode lasers, which also have frequency instability errors. We can lock frequencies of these third-party light sources to the modes of the femtosecond laser which is stabilized to the precision of the standard radio frequency. To this end, we have stabilized all the modes of the femtosecond laser to the atomic frequency standard by using powerful tools of frequency-domain laser stabilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.224-228
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• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.