• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.

• 대한기계학회논문집B
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• 제31권9호
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• pp.780-789
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• 2007

Lock-on phenomenon in the wake of a circular cylinder is investigated at the Reynolds number of 360 using direct numerical simulation (DNS). To induce lock-on, a streamwise velocity perturbation with a frequency of twice the natural shedding frequency is superimposed on the free stream velocity. The Reynolds stress distributions are investigated to analyze the streamwise force balance acting on the recirculation region and the results are compared with the previous experimental result. When the lock-on occurs, the pressure force on the recirculation region is shown to increase mainly due to the reversal of the Reynolds shear stress distribution, which is consistent with our previous results using PIV measurement. It is also shown that, with the lock-on, the strength of the primary vortices increases whereas that of the secondary vortices decreases significantly. Further, under the lock-on condition the wavelength of the secondary vortices increases by as much as 2.5 times.

• 한국전산구조공학회논문집
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• 제29권1호
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• pp.9-18
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• 2016

고층빌딩이나 해양 라이저와 같은 세장 구조물은 구조시스템의 동적 불안정의 주요 원인인 와류유기진동(vortex-induced vibration, VIV)에 의한 동하중에 매우 취약하다. 와류유기진동이 라이저의 고유진동수 영역에서 발생하는 경우 Lock-in현상으로 피로파괴의 우려가 있다. 본 논문에서는 Lock-in 영역에서 구조물과 유동의 동적거동에 대한 수치해석을 다루었으며, 유동조건 변화에도 불구하고 공진 주파수가 유지되는 현상에 대해 분석하였으며, 유입유동에 대해 수직방향으로 자유진동하는 1자유도의 2차원 원형실린더 단면에 대한 비정상 층류를 가정하였다. 각 시간 단계에서 물체의 움직임을 고려하여 유동장 격자를 재생성하며 비정상 유동과 물체의 운동에 대한 지배방정식을 순차적으로 수치해석하여 유체-구조 연성해석을 수행하였다. 결과는 선행연구와 잘 일치함을 보여주었고, Lock-in 현상에 대한 특성을 잘 나타내었다. Lock-in 영역에서는 양력뿐만 아니라 항력도 크게 증가함을 보여주었으며, 실린더의 수직변위는 직경의 20%까지 이름을 나타내었다. 양력과 수직변위의 상관분석을 통해 실린더가 Lock-in 영역에서 양력과 수직변위의 위상차가 동기로부터 반동기로 천이함을 확인하였으며, 이러한 변화가 Lock-in 영역에서 나타나는 공진거동의 원인이 되는 것으로 판된되었다.

• 비파괴검사학회지
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• 제32권3호
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• pp.276-283
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• 2012

In this study, it was studies the utilization of LIT(lock-in infrared thermography) which can detect defects in welded parts of ship and offshore structures. Quantitative analysis was used through methods of filtering and texture measurement of image processing techniques to find the optimized experimental condition. We verified reliability in our methods by applying image processing techniques in order to normalize evaluations of comparative images that show phase difference. In addition, low to mid exposure showed good results whereas high exposure did not provide significant results in regards to intensity of light exposure on surface. Lock-in frequency was satisfactory around 0.1 Hz regardless of intensity of light source we had. In addition, having the integration time of thermography camera inversely proportional to intensity of exposed light source during the experiment allowed good outcome of results.

• 대한조선학회논문집
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• 제42권4호
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• pp.368-378
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• 2005

The effects of rotary oscillation on the unsteady laminar flow past a circular cylinder. are numerically investigated in the present study. The numerical solutions for the 20 Wavier-Stokes equation are obtained using a finite volume method Tn the framework of an overlapping grid system. The vortex formation behind a circular cylinder and the hydrodynamics of wake flows for different rotary oscillation conditions are analyzed from the results of numerical simulation. The lock-on region is defined as the region that the natural shedding frequency due to the Karmann Vortex shedding and the forcing frequency due to the forced oscillating a cylinder are nearly same, and the quasi-periodic states are observed around that region. At the intersection between lock-on and non-lock-on region the shedding frequency is bifurcated. After the bifurcation, one frequency fellows the forcing frequency($S_f$) and the other returns to the natural shedding frequency($St_0$). in the quasi-periodic states, the variation of magnitudes and relevant phase changes of $C_L$ with forcing phase are examined.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.79-82
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• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권10호
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• 전자공학회논문지
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• 제50권10호
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• pp.76-81
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• 2013

130nm CMOS 공정 라이브러리를 이용하여 125MHz로 동작하는 새로운 위상 주파수 검출기 기반 DPLL을 설계하였다. 이 DPLL은 중간 주파수대 응용을 위해 지터와 록 시간을 줄이려고 전형적인 DPLL에 반전 에지 검출기를 포함하고 있다. XOR 기반 반전 에지 검출기들은 출력을 보다 빨리 변화시키기 위하여 기준 신호보다 빠른 전이를 얻는데 사용된다. HSPICE 시뮬 레이터는 모의실험을 위해 Cadence환경에서 사용되었다. 제안된 위상 주파수 검출기를 가진 DPLL의 성능은 종래의 위상 주 파수 검출기를 가진 것의 성능과 비교하였다. 종래의 PLL은 약 0.1245 ns의 최대 지터를 가지고 록 하는데 최소 $2.144{\mu}s$가 걸린 반면에, 제안한 검출기를 가진 PLL은 약 0.1142 ns의 최대 지터를 가지고 록 하는데 $0.304{\mu}s$가 걸린다.

• 대한기계학회논문집B
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• 제31권8호
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• pp.702-710
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• 2007

Direct numerical simulation (DNS) is performed to investigate suppressed wake transition and occurrence of lock-on in the wake of a circular cylinder disturbed by sinusoidal perturbation at the Reynolds number of 220 (A-mode instability regime). The sinusoidal perturbation, of which the frequency is near twice the natural shedding frequency, is superimposed on the free stream velocity. It is shown that the wake transition behind the circular cylinder can be suppressed due to the perturbation of the free stream velocity. This change causes a jump in the Strouhal number from the value corresponding to A-mode instability regime to the value corresponding to retarded wake transition regime (extrapolated from laminar shedding regime) in the Strouhal-Reynolds number relationship. As a result, vortex shedding frequency is locked on the perturbation frequency depending not on the natural shedding frequency but on the modified shedding frequency.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권1호
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.