• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.199-199
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• 2003

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.3
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• pp.322-331
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• 2013

This paper describes the development of the pilot plant of distributed intelligent management system for a microgrid. For optimal control and management of microgrids, intelligent agents area applied to the microgrid management system. Each agent includes intelligent algorithms to make decisions on behalf of the corresponding microgrid entity such as distributed generators, local loads, and so on. To this end, each agent has its own resources to evaluate the system conditions by collecting local information and also communicating with other agents. This paper presents key features of the data communication and management of the developed pilot plant such as the construction of mesh network using local wireless communication techniques, the autonomous agent coordination schemes using plug-and-play functions of agents and contract net protocol (CNP) for decision-making. The performance of the pilot plant and developed algorithms are verified via real-time microgrid test bench based on hardware-in-the-loop simulation systems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.39-46
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• 1999

In this paper, we propose new hardware architecture of a fast searcher for an initial code acquisition in wideband CDMA wireless local loop systems. The proposed searcher uses double-dwell serial search algorithm and has N active correlators for the high performance code acquisition. Since the N active correlators are designed with pipelined architecture, it is possible to reduce the hardware complexity with only one energy calculation. Our architecture is designed using VHDL to meet wideband CDMA wireless local loop standard and verified under JTC wideband channels. Average code acquisition time of the proposed fast searcher which has 16 correlators is about 40 seconds in case of initial installation and 0.16 seconds when a base station is known. The verified fast searcher is synthesized with in $0.6\mu\textrm{m}$ LG library. The synthesized searcher has 15.8K rates when the number of 4he correlators is 16.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.50-57
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• 2000

By supporting wireless communication technology, there is gradually expansion of the commercial application for Wireless Local Loop(WLL) technology, which is to replace existing telephone line with wireless one. The WLL system application helps a operator to have merits of the installation and maintenance of line and also a subscriber to make a high speed value-added service. As mentioned above reasons for both sides, many manufactories and operators are concerned with development and application respectively. This paper presents hardware implementation of Radio Port Controller(RPC) and also describes the system configuration, functions, and Inter Processor Communication(IPC) structure of RPC. We performed inter-module communication test via IPC backplane bus. And inter-module integration test also completed through data communication and signal waveform measurement repeatedly.

• Nuclear Engineering and Technology
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• v.49 no.1
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• pp.103-112
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• 2017

Application of the supercritical condition in reactor core cooling needs to be properly justified based on the extreme level of parameters involved. Therefore, a numerical study is presented to compare the thermalhydraulic performance of supercritical and single-phase natural circulation loops under low-to-intermediate power levels. Carbon dioxide and water are selected as respective working fluids, operating under an identical set of conditions. Accordingly, a three-dimensional computational model was developed, and solved with an appropriate turbulence model and equations of state. Large asymmetry in velocity and temperature profiles was observed in a single cross section due to local buoyancy effect, which is more prominent for supercritical fluids. Mass flow rate in a supercritical loop increases with power until a maximum is reached, which subsequently corresponds to a rapid deterioration in heat transfer coefficient. That can be identified as the limit of operation for such loops to avoid a high temperature, and therefore, the use of a supercritical loop is suggested only until the appearance of such maxima. Flow-induced heat transfer deterioration can be delayed by increasing system pressure or lowering sink temperature. Bulk temperature level throughout the loop with water as working fluid is higher than supercritical carbon dioxide. This is until the heat transfer deterioration, and hence the use of a single-phase loop is prescribed beyond that limit.

• Journal of Korean Institute of Industrial Engineers
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• v.24 no.1
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• pp.77-93
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• 1998

It is discussed how to locate idle vehicles of AGVS on unidirectional guide paths. The problem is modeled as a median location problem on a cyclic network. The characteristics of the optimal location are analyzed and some useful properties are suggested to reduce the solution space. Based on the properties found, several special types of networks - a pure single-loop type, the loop type with a single branching intersection and the loop type with local branching node - are also analyzed as well as the general cyclic network. In each case of the networks, a solution procedure is suggested. Some numerical examples are provided to illustrate the algorithms developed.

• Journal of IKEEE
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• v.17 no.4
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• pp.484-491
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• 2013

In this paper, we proposed an internal multiband loop embedded monopole antenna for mobile handset that could be used for smart phones. The proposed antenna has a volume of 40 mm(W) ${\times}$ 15 mm(L) ${\times}$ 5 mm(H), ground plane size is 40 mm(W) ${\times}$ 80 mm(L), and covers the GSM900 (Global System for Mobile communications : 880-960 MHz), K-PCS (Korea-Personal Communications Service : 1750-1870 MHz), US-PCS (US Personal Communications Service : 1850-1990 MHz), WCDMA (Wideband Code Division Multiple Access : 1920-2170 MHz), Wibro (2300-2390 MHz), Bluetooth (2400-2483 MHz) and WLAN (Wireless Local Area Network : 2400-2483.5 MHz) bands for VSWR (voltage standing wave ration) less than 3. The proposed loop adding design at middle section of longest branch showed wide impedance bandwidth for the lowest resonance frequency band. The proposed antenna have a lowest resonance frequency band from 738 MHz to 1075 MHz for S11 value of -6dB. A HFSS (High Frequency Structure Simulator) of the Ansys Corporation based on a finite element method is employed to analyze the proposed antenna in the design process and to compare the simulation and experimental results.

• ETRI Journal
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• v.34 no.2
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• pp.175-183
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• 2012

Conventional synchronization algorithms for impulse radio require high-speed sampling and a precise local clock. Here, a phase-locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one-tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high-speed ultra-wideband transceiver shows its feasibility, low complexity, and high precision.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.