• Journal of the Korean Society for Precision Engineering
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• v.14 no.9
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• pp.116-123
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• 1997

We have already presented the constraint satisfaction algorithm which could solve the closed loop porblem in constraint network by using local constraint propagation, variable elimination and constraint modularization. With this algorithm, we have implemented a knowledge-based system (intelligent CAD) for supporting machine design interactively. In this paper, we present newer constraint satisfaction algorithm which can solve inequalities or under-constrained problems in constraint network, interactively and effi- ciently. This algorithm is a hybrid type of using both declarative description (constraint representation) and optimization algorithm (Simulated Annealing), simultaneously. The under-constrained problems are represented by constraint networks and satisfied completely with this algorithm. The usefulness of our algorithm will be illustrated by the application to a gear design.

• International conference on construction engineering and project management
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• 2013.01a
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• pp.151-157
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• 2013

Since the sub-prime mortgage crisis from the US in 2008, the Korean housing market has plummeted. However, the deposit prices of the Korean local lease contract, Chonsei, had been increasing. This increase of Chonsei prices can be a threat to low-income people, most of whom prefer to live in houses with a Chonsei contract. In the housing and Chonsei market, there are many stakeholders with their own interest, hence, simple thoughts about housing and Chonsei market, such as more house supply, will decrease house price, would not work in a real complex housing market. In this research, we suggests system dynamics conceptual model which consists of causal-loop-diagrams for the Chonsei market as well as the housing market. In conclusion, the Chonsei price has its own homeostasis characteristics and different price behavior with housing price in the short and long term period. We found that unless government does not have a structural causation mind in implementing policies in the real estate market, the government may not attain their intended effectiveness on both markets.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.47-51
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• 2003

Due to the asymptotic property, deadbeat control which is well used in digital control system can not be applied to the continuous time system. But recently by use of the finite Laplace Transform to transfer function and establishment of some settling conditions, CDBC(Continuous time Deadbeat Control) is studied. For CDBC design, transfer function is constituted with delay elements and then order and interpolation conditions are derived. In other way, digital deadbeat controller is implemented and it's output is changed to continuous type by smoothing elements. In this paper multirate sampling is used and so inner controller is sampled faster than output feedback loop. And End order smoothing elements is placed to the output of digital deadbeat controller. By the multirate sampling overall output response is improved. The controller is impleneted as a serial integral compensator in the forward path and a local feedback compensator introduced into the outpute feedback loop. Matlab Simulink is used for simulation.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.311-316
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• 2010

Esterel is an imperative synchronous language that is used to develop memories, cache controllers, bus interfaces, and so on. An Esterel statement is called schizophrenic if it is executed more than once in an instant. A schizophrenic statement may cause problems when it is translated to hardware circuits; a circuit performs more than one reaction in a clock. Previous works claim that only local signal declarations and parallel statements may cause schizophrenic problems. However, control signals produced by a trap statement or data signals used by emit statements can cause schizophrenia. They are new schizophrenic patterns. Especially, schizophrenic problems caused by emit statements cannot be solved by a loop unrolling technique that is the key idea of previous curing techniques for schizophrenic problems. In this paper, we introduce and define the two schizophrenic problems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• Asian Pacific Journal of Cancer Prevention
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• v.17 no.6
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• pp.2853-2856
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• 2016

Background: Many studies have pointed to strategies to cope with patient anxiety in colposcopy. Evidence shows that patients experienced considerable distress with the large loop excision of transformation zone (LLETZ) procedure and suitable interventions should be introduced to reduce anxiety. This study aimed to investigate the effects of music therapy in patients undergoing LLETZ. Materials and Methods: A randomized controlled trial was conducted with patients undergoing LLETZ performed under local anesthesia in an out patient setting at Ramathibodi Hospital, Bangkok, Thailand, from February 2015 to January 2016. After informed consent and demographic data were obtained, we assessed the anxiety level using State Anxiety Inventory pre and post procedures. Music group patients listened to classical songs through headphones, while the control group received the standard care. Pain score was evaluated with a visual analog scale (VAS). Statistical analysis was conducted using Pearson Chi-square, Fisher's Exact test and T-Test and p-values less than 0.05 were considered statistically significant. Results: A total of 73 patients were enrolled and randomized, resulting in 36 women in the music group and 37 women in the non-music control group. The preoperative mean anxiety score was higher in the music group (46.8 VS 45.8 points). The postoperative mean anxiety scores in the music and the non-music groups were 38.7 and 41.3 points, respectively. VAS was lower in music group (2.55 VS 3.33). The percent change of anxiety was greater in the music group, although there was no significant difference between two groups. Conclusions: Music therapy did not significantly reduce anxiety in patients undergoing the LLETZ procedure. However, different interventions should be developed to ease the patients' apprehension during this procedure.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1407-1417
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• 1996

In recent researches on thread partitioning algorithms break a thread at the long latency operation and merge threads to get the longer threads under the given constraints. Due to this limitation, even a program with little parallelism is partitioned into small-sized threads and context-swithings occur frequently. In the paper, we propose another method array localization about the array name, dependence distance(the difference of accessed element index from loop index), and the element usage that indicates whether element is used or defined. Using this information we can allocate array elements to the node where the corresponding loop activation is executed. By array localization, remote accesses to array elements can be replaced with local accesses to localized array elements. As a resuit,the boundaries of some threads are removed, programs can be partitioned into the larger threads and the number of context switchings reduced.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2526-2533
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• 2015

In this paper, a design method for a compact dual-band coplanar waveguide-fed slot antenna using SRR(split-ring resonator) conductor is studied. The SRR conductor is loaded inside a rectangular slot of the proposed antenna for dual-band operation. When the SRR conductor is inserted into the slot, the original rectangular slot is divided into a rectangular loop region and a rectangular slot region, and frequency bands are created by the loop and slot, separately. A prototype of the proposed dual-band slot antenna operating at 2.45 GHz WLAN band and 3.40-5.35 GHz band is fabricated on an FR4 substrate with a dimension of 30 mm by 30 mm. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.38-2.51 GHz and 3.32-5.38 GHz for a voltage standing wave < 2, and measured gain is 1.7 dBi at 2.45 GHz, and it ranges 2.4-3.2 dBi in the second band.