• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• The Journal of the Korea Contents Association
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• v.7 no.5
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• pp.102-109
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• 2007

This is an analysis study about the pictorial frame of Georges Schwizgebel's animation "The Subject of Picture", focusing on Deleuze's frame theory. First of all, the shapes in the frame of the animation is the representation of the tactile sensation from the erased vestiges of the characters. It shows the metamorphosis of the erased vestiges of the shapes by Deleuze's sensibility theory. Besides, the layout of the animation's background has similar property with the aplat which was mentioned by Deleuze. It means that the background of the animation correspond to the aplat which is other boundary different from reality, and the character which has the minimum embodiment about the object makes the shape newly through the distortion of the shape. Secondly, as the problem of frames in terms of the continuity of time, the meaning in Schwizgebel's animation is created by the relation between each frame. It means that the depiction of the shape itself by the composition between each frame is composed of the frame. Eventually, Schwizgebel's work is the animation which has the characteristic of the modem cinema and is the crystal depiction that deviates from rules and logics of the object which was mentioned by Deleuze.

• 한국정보교육학회:학술대회논문집
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• 2011.01a
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• pp.91-101
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• 2011

The purpose of this paper is to quickly identify school parents, teachers, students, community needs and opinions for curriculum organizing and the implementation of an online survey system for operating educational activities. Online survey system should be implemented based on Limesurvey to reduce costs and administrative costs. Limesurvery is available without the development of the separate program and offers the form of web-based template system, complete design, layout. Also, Limesurvey offers basic statistical analysis of survey data. Limesurvey can be executed by installing the program on a web hosting, typing database information. Limesurvey can be made a graph of the statistical results. Besides, Limesurvery can be stored in the form of HTML, Word, Excel, CSV Files and can be stured as basic datas for SPSS or PASW, R data, other statistical processing programs. If we could be operate Limesurvey in the form of open source-based survey program in elementary school, we could be reduced teacher's unnecessary work for statistics and overcame the problem of offline survey system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Tunnel and Underground Space
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• v.29 no.6
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• pp.480-507
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• 2019

This paper aims at optimizing the auxiliary ventilation system in large-opening limestone mines with unducted fans. An extensive CFD and also site study were carried out for optimization at the blind entries. The fan location, operating mode, and layout are the parameters for optimization. Since the jet stream discharged from the auxiliary fan is flowing faster than 15 m/s in most of the cases, the stream collides with floor, sides or roof and even with the jet stream generated from the other fan placed upstream. Then, it is likely to lose a large portion of its inertial force and then its ventilation efficiency drops considerably. Therefore, the optimal fan installation interval is defined in this study as an interval that maximizes the uninterrupted flowing distance of the jet stream, while the cross-sectional installation location can be optimized to minimize the energy loss due to possible collision with the entry sides. Consequently, the optimization of the fan location will improve ventilation efficiency and subsequently the energy cost. A number of different three-dimensional computational domains representing a full-scale underground space were developed for the CFD study. The velocity profiles and the CO concentrations were studied to design and optimize the auxiliary ventilation system without duct and at the same time mine site experiments were carried out for comparison purposes. The ultimate goal is to optimize the auxiliary ventilation system without tubing to provide a reliable, low-cost and efficient solution to maintain the clean and safe work environment in local large-opening underground limestone mines.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of Korean Tunnelling and Underground Space Association
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• v.24 no.6
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• pp.637-658
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• 2022

TBM tunnel is simple with the iterative process of excavating the ground, building a segment ring-build, and backfilling. Drill & Blast, a conventional tunnel construction method, is more complicated than the TBM tunnel and has some restrictions because it repeats the inspection, drilling, charging, blasting, ventilation, muck treatment, and installation of support materials. However, the preparation work for excavation requires time and cost based on a very detailed plan compared to Drill & Blasting, which reinforces the ground and forms a tunnel after the formation of tunnel portal. This is because the TBM equipment for excavating the target ground determines the success or failure of the construction. If the TBM, an expensive order-made equipment, is incorrectly configured at the assembly stage, it becomes difficult to excavate from the initial stage as well as the main excavation stage. When the assembled shield TBM equipment is dismantled again, and a situation of re-assembly occurs, it is difficult throughout the construction period due to economic loss as well as time. Therefore, in this study, the layout and plan of the site and the assembly process for each major part of the TBM equipment were reviewed for the assembly of slurry shield TBM to construct the largest diameter road tunnel in domestic passing through the Han River and minimized interference with other processes and the efficiency of cutter head assembly and transport were analyzed and improved to suit the site conditions.