• Title/Summary/Keyword: layout model

Search Result 565, Processing Time 0.042 seconds

Machine Learning Based Architecture and Urban Data Analysis - Construction of Floating Population Model Using Deep Learning - (머신러닝을 통한 건축 도시 데이터 분석의 기초적 연구 - 딥러닝을 이용한 유동인구 모델 구축 -)

  • Shin, Dong-Youn
    • Journal of KIBIM
    • /
    • v.9 no.1
    • /
    • pp.22-31
    • /
    • 2019
  • In this paper, we construct a prototype model for city data prediction by using time series data of floating population, and use machine learning to analyze urban data of complex structure. A correlation prediction model was constructed using three of the 10 data (total flow population, male flow population, and Monday flow population), and the result was compared with the actual data. The results of the accuracy were evaluated. The results of this study show that the predicted model of the floating population predicts the correlation between the predicted floating population and the current state of commerce. It is expected that it will help efficient and objective design in the planning stages of architecture, landscape, and urban areas such as tree environment design and layout of trails. Also, it is expected that the dynamic population prediction using multivariate time series data and collected location data will be able to perform integrated simulation with time series data of various fields.

A Comparison of Flow Efficiency between To/From Ratio Method and Minimal Backward-Flow Model in a Linear Machine Layout (선형기계배치에서 To/From 방법과 최소역흐름 모형의 효율비교)

  • Won, You-Dong
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.20 no.44
    • /
    • pp.369-376
    • /
    • 1997
  • 제조셀에서의 기계배치 문제는 매우 중요한 문제 중의 하나이다. 제조셀에서의 기계매치 형태는 크게 선형배치 방법과 네트워크형배치 방법의 두 가지가 있다. 본 논문에서는 선형배치 방법에 대하여 검토한다. 선형배치를 위한 가장 일반적인 방법은 to/from 비율에 의한 방법이다. 본 논문에서는 최소역흐름모형을 제시하여 to/from 비율에 의한 방법과 비교한다. 비교 결과 최소역흐름모형에 의한 선형기계배치의 경우가 to/from 비율에 의한 방법보다 총역흐름 이동거리를 상당히 감소시키는 것으로 나타났다.

  • PDF

Facilities Location Allocation of Ulsan Industrial Technology Research Park Using SLP Procedures (SLP를 이용한 산업기술연구단지 최적공간배치 결정 - 울산산업기술연구단지를 중심으로 -)

  • 김복만;최성운
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.21 no.48
    • /
    • pp.1-14
    • /
    • 1998
  • This paper describes a study which was undertaken in Ulsan City. The modified SLP procedures consider the quantitative flow aspect of the facilities layout problem as well as the qualitative closeness rating aspect. Conclusions are drawn as to the effectiveness of the proposed model in providing Ulsan City with better means of making the facilities location allocation decision for Industrial Technology Research Park.

  • PDF

Computer Generation of Equivalent Circuit for Unit Cell of LCD-TV

  • Yoon, Suk-In;Jung, Chan-Yong;Won, Tae-Young
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2006.08a
    • /
    • pp.739-742
    • /
    • 2006
  • In this paper, we propose a method for automatic generation of equivalent circuit for unit cell of LCDTV. In order to extract a circuit model, computer program generates electrical connectivity of resistors and capacitors from the layout through pattern analysis with electrode and port information. For combining two types of independent equivalent circuits, we propose a node insertion algorithm. As a consequence, we can generate an equivalent RC circuit without increasing the capacitive elements.

  • PDF

DC Characteristics of InP/InGaAs HPT's with an Optically Transparent ITO Emitter electrode (광학적 투명성을 가진 ITO를 에미터 전극으로 사용한 InP/lnGaAs HPT's의 DC 특성 분석)

  • 강민수;한교용
    • Proceedings of the IEEK Conference
    • /
    • 2001.06b
    • /
    • pp.13-16
    • /
    • 2001
  • InP/InGaAs Heterojunction phototransistors(HPT's) with an optically transparent ITO emitter electrode were fabricated and characterized. At the same time, heterojuntion transistors(HBT's) having the same device layout were fabricated. By comparison with InP/InGaAs HBT's, the do characteristics of InP/InGaAs HPT's showed the similar electrical charateristics of HBT's. the model parameters of the device were extracted and compared.

  • PDF

A Simulation Analysis of Productivity Increasement Effect of JIT System Application (JTL시스템 적용에 의한 생산성향상 효과의 시뮬레이션 분석)

  • 신현표;구일섭
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.18 no.34
    • /
    • pp.115-121
    • /
    • 1995
  • The objective of this study is to develope an effectiveness measurement technique for U-shaped JIT production line by computer simulation. A small and medium sized automobile brake master cylinder manufacturing plant is studied for productivity improvement The production line is analysed and improved by applying Low Cost Automation, special jigs and fixtures, and facilities layout changes. An experimental simulation model is built using SIMAN(SIMulation ANalysis) simulation software for the production system analysis.

  • PDF

A Simulation Model for Capacity Design of a Manufacturing Process for Bearing (베어링 제조공정 용량설계를 위한 시뮬레이션 모델)

  • 문덕희;장구길
    • Proceedings of the Korea Society for Simulation Conference
    • /
    • 2001.05a
    • /
    • pp.20-24
    • /
    • 2001
  • 공장을 신축할 경우 일반적인 설비계획 절차에 따라 제품설계, 공정 설계, 용량설계를 거쳐 Layout 설계로 이어지게 된다. 이 과정에서 용량설계는 공장에 설치할 기계의 적정 대수를 결정하고, 각 공정 사이의 재공품을 예측하여 저장장소의 적정 면적을 결정한다는 점에서 매우 중요한 단계라 하겠다. 이 논문에서는 볼베어링을 제조하는 D사의 신축공장 설계시 수행했던 용량설계를 위한 시뮬레이션에 대한 사례를 소개하고자 한다. 시뮬레이션의 주요 관심사는 당초 회사측에서 제시했던 설비들의 수량이 회사의 생산목표를 달성할 수 있는 지에 대한 검토와, 이를 해결하기 위한 방향 제시, 공정별 재공품에 대한 예측 등이다.

  • PDF

Automatic Layout Design of CMOL FPGA (CMOL FPGA 자동 레이아웃 설계)

  • Kim, Kyo-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.11
    • /
    • pp.56-64
    • /
    • 2007
  • We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.

A New TWA-Based Efficient Signal Integrity Verification Technique for Complicated Multi-Layer RLC Interconnect Lines (복잡한 다층 RLC 배선구조에서의 TWA를 기반으로 한 효율적인 시그널 인테그러티 검증)

  • Jo Chan-Min;Eo Yung-Seon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.7 s.349
    • /
    • pp.20-28
    • /
    • 2006
  • A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

Shear and tensile behaviors of headed stud connectors in double skin composite shear wall

  • Yan, Jia-Bao;Wang, Zhe;Wang, Tao;Wang, Xiao-Ting
    • Steel and Composite Structures
    • /
    • v.26 no.6
    • /
    • pp.759-769
    • /
    • 2018
  • This paper studies shear and tensile behaviors of headed stud connectors in double skin composite (DSC) structure. Firstly, 11 push-out tests and 11 tensile tests were performed to investigate the ultimate shear and tensile behaviors of headed stud in DSC shear wall, respectively. The main parameters investigated in this test program were height and layout of headed stud connectors. The test results reported the representative failure modes of headed studs in DSC structures subjected to shear and tension. The shear-slip and tension-elongation behaviors of headed studs in DSC structures were also reported. Influences of different parameters on these shear-slip and tension-elongation behaviors of headed studs were discussed and analyzed. Analytical models were also developed to predict the ultimate shear and tensile resistances of headed stud connectors in DSC shear walls. The developed analytical model incorporated the influence of the dense layout of headed studs in DSC shear walls. The validations of analytical predictions against 22 test results confirmed the accuracy of developed analytical models.