• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (B)
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of the Korean Society for Precision Engineering
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• 제20권11호
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• pp.41-46
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• 2003

The objective of this paper is to present a methodology for automatically balancing multi-cavity injection molds with the aid of flow simulation. After the runner and cavity layout has been designed, the methodology adjusts runner and gate sizes iteratively based on the outputs of flow analysis. This methodology also ensures that the runner sizes in the final design are machinable. To illustrate this methodology, an example is used wherein a 3-cavity mold is modeled and filling of all the cavities at the same time is achieved. Based on the proposed methodology, a multicavity mold with identical cavities is balanced to minimize overall unfilled volume among various cavities at discrete time steps of the molding cycle. The example indicates that the described methodology can be used effectively to balance runner systems for multi-cavity molds.

• Journal of the Korean Operations Research and Management Science Society
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• 제5권1호
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• pp.39-51
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• 1980

This paper deals with the problem of determining the capacity expansion timing and sizes of conduits and feeder cables for a given cable network configuration of a single exchange ares, which minimizes the present worth of total costs. The planning horizon is infinite and the demand of line pairs at each cabinet is assumed to be determininstically growing. As a solution method, the heuristic branch-and-bound algorithm of Freidenfelds and Mclaughlin is elaborated by adding details and some minor modifications, which generates a good near-optimal solution with far less computation than would otherwise be possible. We also develop a computer program, which is shown to be effective and efficient through the test run of an illustrative example.

• Journal of the Korean Institute of Telematics and Electronics
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• 제26권11호
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제33A권12호
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.125-130
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• 2001

Skilled typists can type characters or words without looking at keyboard, relying on the finger's relative position. If the relative positions of the fingers can be identified, a virtual keyboard may be accomplished by applying the concept of "DataGlove" or "FingerRing". The virtual keyboard may be efficient as a new mobile input device supporting QWERTY keyboard layout. For the purpose of investigating skilled typing pattern, in this paper the touch-positions of the fingers are measured with a touchscreen while five skilled typists type a long sentence. From these measurements it can be observed that the groups of touch-positions are classified into alphabet characters. Though there are some overlapped groups we can find constant distances capable of being discriminated among the groups from investigation of the change of touch-position for touch-time. Based on the analysis, the prediction algorithm of the constant distance is proposed and evaluated, which is useful for realization of a portable virtual keyboard.le virtual keyboard.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1161-1164
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제34C권10호
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• pp.8-18
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• 1997

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

• Journal of Industrial Technology
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• 제16권
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• pp.217-230
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• 1996

This paper deals with storage and retrieval policies for S/R machine with capacity constraints in Man-On-Board AS/RS. It is assumed that storage sequence is based on SFC(spacefilling curve) routine and that storage layout is dedicated by storage policies. We present several heuristic algorithms for storage and retrieval policies which minimize total distance travelled by the S/R machine. These algorithms are based on COI, group COI, frequency of order, similarity between items and capacity of S/R machine. Experimental results of 24 combinastorial policies are provided to illustrate the performance of the heuristics under various rack utilization ratios. In storage policies, the results show that algorithms considering both similarity and frequency are better than those with COI as rack utilization is increasing. And algorithm using group COI is superior to others. In retrieval policies, the method with revision expression is shown to be better than others.

• Journal of Institute of Control, Robotics and Systems
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• 제9권9호
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• pp.720-726
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• 2003

A virtual keyboard may be efficient as a new mobile input device supporting QWERTY keyboard layout. As a preliminary study for developing a virtual keyboard, the typing pattern of a skilled human is investigated. In the study the touch-positions of the fingers are measured with a touchscreen while five skilled typists perform typing of long sentences. From these measurements it can be observed that the groups of touch-positions are classified into alphabetic characters. Though there are some mismatches, we can find constant distances capable of being discriminated among the groups. Based on the analysis the prediction algorithm of the constant distance is proposed and evaluated, which is useful for realization of a portable virtual keyboard.