• 한국정밀공학회지
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• 제16권11호
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• pp.139-147
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• 1999

Rapid Prototyping has made a drastic change in all industries which needs to reduce the time for the development of new products. Orientation and packing in rapid prototyping is considered as the most important factors to maximize the utilization of space in the build chamber and reduce build time. However, the decision of these parameter is mainly dependant on the operators's experience. This paper presents the methodology to find the optimal build layout considering an orientation and packing of multiple parts in SLS processing. Each part is represented as a voxel structure to deal with the inefficiency in a bounding box approach. Test results show that the adapted BL algorithm with a genetic algorithm(GA) can be applicable to a real industry.

• ETRI Journal
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• 제45권6호
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• pp.1035-1045
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• 2023

We propose a novel graphics processing unit (GPU) algorithm that can handle a large-scale 3D fast Fourier transform (i.e., 3D-FFT) problem whose data size is larger than the GPU's memory. A 1D FFT-based 3D-FFT computational approach is used to solve the limited device memory issue. Moreover, to reduce the communication overhead between the CPU and GPU, we propose a 3D data-transposition method that converts the target 1D vector into a contiguous memory layout and improves data transfer efficiency. The transposed data are communicated between the host and device memories efficiently through the pinned buffer and multiple streams. We apply our method to various large-scale benchmarks and compare its performance with the state-of-the-art multicore CPU FFT library (i.e., fastest Fourier transform in the West [FFTW]) and a prior GPU-based 3D-FFT algorithm. Our method achieves a higher performance (up to 2.89 times) than FFTW; it yields more performance gaps as the data size increases. The performance of the prior GPU algorithm decreases considerably in massive-scale problems, whereas our method's performance is stable.

• 전자공학회논문지CI
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• 제45권1호
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• pp.37-47
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• 2008

DSP에서 제공되는 주소 생성 유닛은 데이터 패스와 병렬적으로 주소 연산을 수행할 수 있게 해 줌으로써, DSP 코드 생성에 중요한 역할을 한다. 프로그램 변수들의 메모리 레이아웃을 결정하는 문제는 주소 생성 유닛의 기능을 이용하여 주소 연산용 명령어를 줄이는 최적화이다. 메모리 레이아웃 생성 단계와 주소 포인터 할당 단계로 구분 되는 이 최적화에서 본 논문은 주소 연산 코드의 수가 최소가 되도록 DSP용 코드 생성의 효과적인 주소 포인터 할당 문제를 다룬다. 제안하는 알고리즘은 고정된 메모리 레이아웃을 가질 때 주소 포인터 할당을 수행하는 기존의 알고리즘의 시간 복잡도를 줄이는 기법이다. 메모리 크기와 수행 시간을 줄이기 위해 알고리즘을 수행할 때 핵심적인 요소들만을 고려하도록 강한 가지치기 방법을 사용하였다. 또한 주소 포인터 할당 문제는 메모리 레이아웃에 영향을 크게 받는 문제이기 때문에 본 논문은 주어진 메모리 레이아웃을 갱신하여 반복적으로 성능을 개선하는 방법을 제안한다. 약 3,000여개의 실제 프로그램으로부터 얻은 변수 접근 시퀀스를 제공하는 OffsetStone 벤치마크를 이용한 실험결과를 통해 본 논문에서 제안한 기법과 알고리즘을 테스트 했다. 제안한 방법은 전통적인 방법보다 평균 25.9%의 적은 주소 코드를 생성해 냄을 보인다.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권5호
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• pp.350-354
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• 2009

임베디드 시스템에서 프로그램 성능을 향상시키기 위해서는 시스템의 하드웨어를 이해하고 활용하는 것이 중요하다. 특히 메모리 서브시스템에 대한 이해는 프로그램을 주어진 하드웨어에 최적화하여 성능을 향상시키는 데 큰 역할을 한다. 본 논문에서는 cache, TLB, DRAM과 같은 메모리 서브시스템의 파라미터를 자동적으로 검출하는 기존의 알고리즘을 임베디드 시스템에 적용해 보고, 새롭게 메모리 뱅크 개수 검출 알고리즘을 제안한다. 제안한 알고리즘은 실제 여러 가지 임베디드 시스템 환경에서 실험을 통해 검증하였고, 실험 결과 메모리 서브시스템의 파라미터를 정확히 검출해 낼 수 있는 것을 확인하였다.

• Journal of Mechanical Science and Technology
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• 제14권3호
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• pp.306-313
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• 2000

The homogenization method and the density function method are common approaches to evaluate the equivalent material properties for design cells composed of matter and void. In this research, using a new topology optimization method based on the homogenized material with a penalty factor and the chessboard prevention strategy, we obtain the optimal layout of a structure for the natural frequency of a designated mode. The volume fraction of nodes of each finite element is chosen as the design variable and a total material usage constraint is imposed. In this paper, the subspace method is used to evaluate the eigenvalue and its corresponding eigenvector of the structure for the designated mode and the recursive quadratic programming algorithm, PLBA algorithm, is used to solve the topology optimization problem.

• 한국경영과학회지
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• 제34권3호
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• pp.43-53
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• 2009

The pallet loading problem(PLP) requires the best orthogonal layout that loads the maximum number of identical boxes(small rectangle) onto a pallet(large rectangle). Since the high pallet utilization saves the distribution and storage costs, many heuristic and exact algorithms have been developed so far. Martins and Dell have found the optimal layouts for the all PLPs less than or equal to 100 boxes except for only 5 problems in their recent research. This paper defines the 'stair structure' and proposes a new exact algorithm applying it. In order to show the priority of the proposed algorithm, computational results are compared to previous algorithms and the optimal layouts for the S unsolved problems are given.

• 한국CDE학회논문집
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• 제4권3호
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• pp.259-268
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• 1999

In order to reduce the cost of product and save the processing time, optimal nesting of two-dimensional part is an important application in number of industries like shipbuilding and garment making. There have been many studies on finding the optimal solution of two-dimensional nesting. The problem of two-dimensional nesting has a non-deterministic characteristic and there have been various attempts to solve the problem by reducing the size of problem rather than solving the problem as a whole. Heuristic method and linearlization are often used to find an optimal solution of the problem. In this paper, theoretical and practical nesting algorithm for rectangular, circular and irregular shape of two-dimensional parts is proposed. Both No-Fit-Polygon and Minkowski-Sum are used for solving the overlapping problem of two parts and the dynamic programming technique is used for reducing the number search spae in order to find an optimal solution. Also, nesting designer's expertise is complied into the proposed algorithm to supplement the heuristic method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1074-1079
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• 1987

We present a fast, constructive algorithm for the automatic placement of standard cells, which consists of two steps. The first step is responsible for cell-row assignment of each cell, and converts the circuit connectivity into a multi-stage graph under to constraint that sum of the cell-widths in each stage of the multi-state graph does not exceed maximum cell-row width. Generatin of feed-through cells in the final layout was shown to be drastically reduced by this step. In the second step, the position of each cell within the row is determined one by one from left to right so that the cost function such as the local channel density is minimized. Our experimental result shows that this algorithm yields near optimal results in terms of the number of feed-through cells and the horizontal tracks, while running about 100 times faster than other iterative procedures such as pairwise interchange and generalized force directed relaxation method.

• 대한안전경영과학회지
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• 제10권4호
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• pp.337-342
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• 2008

This paper investigates the optimal nesting system for a board. A hybrid method is used to search the optimal solution for rectangular nesting problem. This method is composed of heuristic approach algorithm. An engineer's experience of board nesting in which a loss occurred to sheet because of various individual error and diffidence. So, item layout at resource sheet were evaluated in engineering algorithm logic in which specially designed was installed. The nesting system consists of Lisp and Visual Basic. The system was controlled by AutoCAD so as to best item batch path test.