• 전자공학회논문지A
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• 제29A권9호
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권4호
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• pp.163-173
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• 2005

The conventional optimization study for electromagnetic systems has been mostly on the shape or size optimization. The goal for these optimization methods is to improve performance of electromagnetic systems by optimizing the interface shape of two different materials while their given layout or initial topology are held. The feasible topology can be diverse and an appropriate topology will give much better design results. In this paper we propose a theory and an algorithm for topology optimization of electromagnetic systems, which are based on the finite element method. The topology optimization technique employes a direct searching method of sensitivity analysis in which the information of material sensitivity is used. Two numerical examples of a switched reluctance motor and an electrostatic actuator of MEMS are tested and their design results show that the optimization method is valid and useful for the topology and basic layout design of electromagnetic systems.

• 대한전자공학회논문지
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• 제24권2호
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• 한국전자통신학회논문지
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• 제15권1호
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• pp.61-70
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• 2020

본 연구에서는 근무자의 주관적인 판단으로 이루어지는 기존의 좌석배치 방법을 보완하고 근무효율성을 높이기 위한 IOT 기반 데스크 배치 방안을 제안하였다. 경량화 된 사물 인터넷 시스템을 근무장 데스크 배치에 도입하여 근무자 좌석 배치 추천을 합리적으로 보조하기 위하여 데스크의 업무상태를 알아내기 위한 센서의 기능과 종류와 네트워크 프로토콜을 결정하였고 데스크 배치를 위한 근무형태 인지 자료 수집 방법을 제안하였다. 획득한 데이터를 이용하여 좌석배치 추천방안을 결정 할 때, Block Stacking에서 사용하는 알고리즘을 활용하였다. 그 결과 사물인터넷 환경에서 합리적인 데스크 배치를 위한 산술적 근거를 제시할 수 있었으며, 향후 근무자들의 선호도에 더하여 근무형태를 근거로 하는 진보된 유연 좌석제에 적용할 수 있음을 보였다.

• 교육시설 논문지
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• 제19권1호
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• pp.37-44
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• 2012

This study developed an algorithm to predict the most efficient evacuation protocol in an elementary school that has an irregular type of architectural planning. The assumption of this study takes a stand point that today's elementary schools are designed in unusual and irregular floor type and, therefore, past architect's knowledge regarding efficient evacuation will no longer effective to save lives. In this regard, this study applied an algorithm that is especially designed to find appropriate locations in general in the field of industrial engineering, which has been proven for many decades. Furthermore, this study not only adapted an engineering model but also conversed to examine spatial relationship and added the concept of group evacuation, which will delay the whole evacuation process, in the tested algorithm to make it more architectural. Consequently, this study compared its outcome with an existing elementary school and questioned its effectiveness in evacuation process based on the algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
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• pp.139-142
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• 2000

In this paper, the ADI (Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and designed the architecture through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using 0.6$\mu\textrm{m}$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• 산업경영시스템학회지
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• 제34권1호
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• pp.33-41
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• 2011

This paper considers a topological optimization of a network design with mean packet delay and node connectivity constraints. The objective is to find the topological layout of links, at minimal cost. This Problem is known to be NP-hard. To efficiently solve the problem, a scatter search algorithm is proposed. An illustrative example is used to explain and test the proposal approach. Experimental results show evidence that the proposal approach performs more efficiently for finding a good solution or near optimal solution in comparison with a genetic approach.

• 한국산업정보학회논문지
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• 제18권4호
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• pp.81-87
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• 2013

IT 기술의 발달과 인터넷의 확산으로 웹 접근성에 대한 중요성이 극대화 되고 있으며, 그에 따라 다양한 웹 접근성 관련 연구가 진행되고 있다. 특히 데이터 테이블과 레이아웃 테이블 용도로 사용되는 "Table 요소"는 자동화평가도구의 평가에서 많은 문제점을 가지고 있다. 이에 본 연구에서는 웹 접근성 지침을 기반으로 "Table 요소"에 대한 개선된 평가 알고리즘을 제시하고 그 타당성을 검증하였다.

• 대한전자공학회논문지
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• 제21권4호
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• pp.13-16
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• 1984

본 논문에서는 NAND 또는 NOR 게이트와 같은 기본 셀로 구성되는 1차원 MOS LSI의 칩 면적을 최소화하기 위한 레이아웃 알고리즘을 제안하고 있다. 배열하고자 하는 MOS 게이트들의 최좌측단과 최우측단에 입·출력 신호선을 표시하는 가상 게이트를 각각 설정하여 각 게이트 통과선 수를 최소화함으로써 수평 트랙 수를 최소로 하는 휴리스틱 알고리즘을 제안하고 실제의 논리회로를 택하여 프로그램 실험을 행함으로써 본 논문에서 제안한 알고리즘이 유용함을 보였다.

• Journal of information and communication convergence engineering
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• 제8권6호
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• pp.716-720
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• 2010

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160{\times}192$ pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in $0.35{\mu}m$ 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one.