• Journal of the Korea Society of Computer and Information
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• v.20 no.9
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.5
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• pp.1412-1430
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• 2024

The soft cancellation list (SCANL) decoding algorithm for polar codes runs L soft cancellation (SCAN) decoders with different decoding factor graphs. Although it can achieve better decoding performance than SCAN algorithm, it has high latency. In this paper, a fast simplified SCANL (Fast-SSCANL) algorithm that runs L independent Fast-SSCAN decoders is proposed. In Fast-SSCANL decoder, special nodes in each factor graph is identified, and corresponding low-latency decoding approaches for each special node is propose first. Then, syndrome check aided Fast-SSCANL (SC-Fast-SSCANL) algorithm is further put forward. The ordinary nodes satisfied the syndrome check will execute hard decision directly without traversing the factor graph, thereby reducing the decoding latency further. Simulation results show that Fast-SSCANL and SC-Fast-SSCANL algorithms can achieve the same BER performance as the SCANL algorithm with lower latency. Fast-SSCANL algorithm can reduce latency by more than 83% compared with SCANL, and SC-Fast-SSCANL algorithm can reduce more than 85% latency compared with SCANL regardless of code length and code rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.75-78
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• 2007

Mobile IP provides hand-held devices with mobility which allows the user to do work over the network. However, handover time due transfer between access routers causes network delays and data loss. L2Trigger Handover expects this handover to take place, and executes L3 handover before L2 handover takes place, thereby reducing overall handover latency, although it still is an issue since handover latency between AR is not completely eliminated in L2 trigger handover. In this paper took into consideration where MIH is used in MIPv4 and using MIH Table when handover is about to occur in MN(Mobile Node), thereby pre-fetching data needed by Handover. In this way, when the handover is estimated, it improves the init time that L2trigger had. Furthermore we can find that we can execute the handover with shorten init time in smaller and narrow overlap length

• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.685-687
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• 2004

본 논문에서는 이동 인터넷 환경에서 핸드오프 시, 링크 계층 (L2) 정보를 이용하며 새로 발견한 모바일 에이전트와의 등록 절차를 L2 핸드오프 완료 후 곧바로 수행하는 로우-레이턴시 (Low-Latency) 핸드오프 방안을 제안하고 이를 구현한다. 제안한 방법은 기존 연구들에 비해 추가적인 L2 핸드오프 지연 및 별도 네트워크 구성요소를 필요로 하지 않으며 보다 일반적이고 현실적인 네트워크 환경에서 적용될 수 있는 방안이다. 실험 결과는 제안된 방법이 인프라스트럭처 (infrastructure) 모드로 설정된 무선 랜에서 모바일 IP의 핸드오프 지연을 크게 개선하여 이동 인터넷 환경의 실시간 멀티미디어 서비스에 적합함을 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.991-1001
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• 2003

CCFH(Candidatecasting Fast Handoff) algorithm excels the performance of existing fast handoff schemes using multicasting in terms of handoff latency and B/W efficiency. The scheme uses L2 information(BSSID) at Wireless LAN and starts multicasting before L2 handoff. So it can reduce L3 handoff latency. At this article, we would show that Candidatecasting Fast Handoff Scheme is clearly new scheme using L2 information and has the good performance.

• International Journal of Contents
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• v.4 no.3
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• pp.29-34
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• 2008

Fast handover is essential to support seamless multicast service in MIPv6. To reduce handover latency of multicast, there are two handover mechanisms, one is M-FMIP that prepares fast L3 handover before L2 handover and the other is M-HMIP that performs local area mobile multicast management. This paper proposes M-FHMIP that integrates an advantage of M-FMIP and M-HMIP, and analyzes the multicast handover latency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.78-82
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• 2015

General-purpose graphics processing units (GPGPUs) provide tremendous computational and processing power. Despite the latency hiding mechanism, a GPU architecture requires high memory bandwidth and lower latency between computational units and the memory system. For this reason, the current GPU architecture has private L1 caches in each core and a shared L2 cache to increase performance by reducing memory latency. But in some cases, this CPU-like cache design is not suitable for GPGPUs. In this paper, we analyze detailed cache performance related to GPGPU application characteristics, and suggest technical alternatives for the GPGPU architecture as future work.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.25-33
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• 2004

Mobile IP Low Latency Handoffs(l) allow greater support for real-time services on a Mobile IP network by minimizing the period of time when a mobile node is unable to send or receive IP packets due to the delay in the Mobile IP Registration process. However, on Mobile IP network with AAA servers that are capable of performing Authentication, Authorization, and Accounting(AAA) services, every Registration has to be traversed to the home network to achieve new session keys, that are distributed by home AAA server, for a new Mobile IP session. This communication delay is the time taken to re-authentication the mobile node and to traverse between foreign and home network even if the mobile node has been previously authorized to old foreign agent. In order to reduce these extra time overheads, we present a method that performs Low Latency Handoffs without requiring further involvement by home AAA server. The method re-uses the previously assigned session keys. To provide confidentiality and integrity of session keys in the phase of key exchange between agents, it uses a key sharing method by gateway foreign agent that performs a trusted thirty party. The proposed method allows the mobile node to perform Low Latency Handoffs with fast as well as secure operation.

• Journal of Biomedical Engineering Research
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• v.17 no.2
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• pp.221-226
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• 1996

Tendon reflex responses generated from mechanical stimulus had been studied for quantitative analysis of activity of tendon reflex, especially patellar tendon reflex responses are known to be a criterion for diagnosing the L3 or L4 radiculopathy. In this paper, we developed a digital signal processing system for analysis of the tendon reflex response. The system parameter, i.e., $\textit{sampling frequency, pre-amplification gain, input channel and filter bank}$ are selected by Using software switches. From the view points of flexibility, the system hardware is connected to an IBM PC for analyzing the tendon reflex parameters, amplitude, latency duration We applied the proposed system to the analysis of the patellar tendon reflex reponses. In the experiment, we measured latency, duration, amplitude of the reflex action potentials generated from vastus medialis, vastus lateralis and rectus femoris that compose quadriceps, and the measured data are analyzed througll the ANOVA test which has 5% significant level. As a result, we showed that the mean amplitude of reflex action potential at the vastus lateralis is larger than any other muscle and the mean latency of the reflex action potential at the rectus femoris is shorter than any other muscle.