• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.534-537
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• 1998

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.240-242
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• 1993

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.103-110
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• 1995

Trench-Gate SOI LIGBT with improved latch-up capability has been proposed and verified by MEDICI simulation. The new SOI LIGBT exhibits 6 time larger latch-up capability of the new device is almost preserved independent of lifetime. the large latch-up capability of the new SOI LIGBT may be realized due to the fact that the hole current in the new device would bypass through the shorted cathode contact without passing the p-well region under the n+ cathode. Forward voltage drop is increased by 25% when a epi thickness is 6$\mu$m. However, the increase of the forward voltage is negligible when the epi thickness is increased to 10$\mu$m. It is found that the swithcing time of the new device is almost equal to the conventional devices. Evaluated breakdown voltage of proposed SOILIGBT is 250 V and that of the conventional SOI LIGBT is 240 V, where the thickness of the vuried oxide and n- epi is 3$\mu$m and 6$\mu$m, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1603-1610
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• 1999

본 논문은 CMOS의 latch-up 특성을 개선하기 위한 효과적인 mask 설계 방법에 관한 것이다. Mask의 평면구조와 latch-up 파라메타와의 상관관계를 실물 제작에 의한 실험과 컴퓨터 시뮬레이션에 의해 도출하였으며, guard ring의 효과에 대해서도 비교 분석하였다. 실험 결과, 수평구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)이 디자인룰에 반비례하였으며, 수직구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)은 디지인룰과 무관하였다. 스위칭전압과 유지전류는 디자인룰에 비례하였다. Guard ring은 latch-up의 가능성을 줄이는 데 상당한 효과가 있었음이 확인되었으며, Guard ring이 없는 경우에 비하여 전류증폭률의 곱($\beta$n$\beta$n)이 약 31% 감소, 유지전류는 약 25%가 향상됨을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.203-205
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• 2004

A soft error rate neutrons is a growing problem for terrestrial integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.

• Journal of Applied Reliability
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• v.14 no.3
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• pp.147-151
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• 2014

An actuator latch device of a hard disk drive is installed for locking an actuator to hold a magnetic head parked in a parking zone. Applying an external force to the drive, the head can move away from the parking zone and destroy data on the disk. A magnet latching mechanism is used to prevent the actuator from moving when the computer is not in use. A permanent magnet holds the actuator when the head is in the parking zone. When the computer is turned on, the actuator has to overcome the latch magnet in order to move. A stronger latch magnet will hold the actuator adequately, but the actuator will not be released when unlocking is required. A breakthrough solution is needed to improve the reliability of the drive without any deterioration of its performance. In order to obtain the idea for resolving this technical contradiction, we analyse patents for actuator latch device of a hard disk drive. A practical way for solving contradictions in product development using TRIZ is proposed in this paper.