• Journal of Korean Academy of Nursing
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• v.47 no.6
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• pp.713-730
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• 2017

Purpose: This study was a systematic review and meta-analysis designed to evaluate the effects of breastfeeding intervention on breastfeeding rates. Methods: Based on the guidelines of the Preferred Reporting Items for Systematic Reviews and Meta-analyses (PRISMA), a systematic search was conducted using eight core electronic databases and other sources including gray literature from January 9 to 19, 2017. Two reviewers independently select the studies and assessed methodological risk of bias of studies using the Cochrane criteria. The topics of breastfeeding interventions were analyzed using descriptive analysis and the effects of intervention were meta-analyzed using the Review Manager 5.2 software. Results: A total of 16 studies were included in the review and 15 were included for meta-analysis. The most frequently used intervention topics were the importance of good latch-on and frequency of feeding and determining adequate intake followed. The pooled total effect of breastfeeding intervention was 1.08 (95% CI 1.03~1.13). In the subgroup analysis, neither pre-nor post-childbirth intervention was effective on the breastfeeding rates at 1, 3, and 6 months, and neither group nor individual interventions had an effect. Only the 1 month breastfeeding rate was found to be affected by the individual intervention with the persistent strategies 1.21 (95% CI 1.04~1.40). Conclusion: Effective breastfeeding interventions are needed to help the mother to start breastfeeding after childbirth and continue for at least six months. It should be programmed such that individuals can acquire information and specific breastfeeding skills. After returning home, there should be continuous support strategies for breastfeeding as well as managing various difficulties related to childcare.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.96-102
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• 2014

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

• Journal of IKEEE
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• v.17 no.2
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• pp.208-213
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• 2013

In this paper, we proposed the novel SCR-based ESD protection circuit with high holding voltage for power clamp. In order to increase the holding voltage, the floating p+ and n+ to n-well and p-well, respectively, in the conventional SCR. The resulting increase of the holding voltage of the our proposed ESD circuit enables the high latch-up immunity. The electrical characteristics including ESD robustness of the proposed ESD circuit have been simulated using Synopsys TCAD simulator. According to the simulation result, the proposed device has higher holding voltage of 4.98 V than that of the conventional SCR protection circuit. Moreover, it is confirmed that the device could have the holding voltage of maximum 13.26 V with the size variation of floated diffusion area.

• Journal of IKEEE
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• v.20 no.3
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• pp.295-298
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• 2016

In this paper, we analysed the properties of the conventional ESD protection devices such as SCR, MVSCR, LVTSCR. The electrical characteristics and the turn-on time properties are simulated by Synopsys T-CAD simulator. As the results, the devices have the holding voltages between 2V and 3V, and the trigger voltage of about 20V with SCR, of about 12V with MVSCR, of about 9V with LVTSCR. The results of the simulation for the turn-on time properties are 2.8ns of SCR, 2.2ns of MVSCR, 2.0ns of LVTSCR. Thus, we prove that LVTSCR has the shortest turn-on time. However, the second breakdown currents(It2) of the devices are 7.7A of SCR, 5.5A of MVSCR, 4A of LVTSCR. This different properties have to be adapted by the operation voltages for I/O Clamps.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.11
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• pp.273-276
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• 1996

In the Total Artificial Heart (TAH) and Ventricular Assist Device (VAD), the size implanting the internal controller into human body is very serious problem. Hence, we need the size reduction of that controller for safe implantation. Using PSD302 chip for microcontroller-based applications, we could decrease the number of components in the digital control board and miniaturize the digital control board. We could replace a ROM, RAM, and a latch with that single chip, so the size of the newly developed board could be half the previous board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of The Korea Institute of Healthcare Architecture
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• v.23 no.4
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• pp.7-15
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• 2017

Purpose: The Korean government has implemented a Barrier Free Certification System since 2008 to create a secure and convenient environment for the socially disadvantaged. The drastic increase in the number of BF-certification facilities is expected due to the revision of the system and increasing the number of certification institutions. An analysis of individual evaluation items needs to be made for the BF-Certification with public confidence. Method: Korean standard, International Standard(ISO/FDIS 21542, 2011), German Standard(DIN 18040-1, 2010), Austrian Standard(${\ddot{O}}NORM$ B 1600, 2017) and Swiss Standard(Norm SIA 500 / SN 521 500, 2009) were investigated and analyzed. A comprehensive improvement plan is proposed by comparing details of the aforementioned standards and the evaluation items of BF-Certification. Results: Many problems arise in applying existing Barrier-free standards due to changes in population structure, environmental change and the use of powered wheelchairs. International standards are being improved to solve these problems. The korean standards also require improving of the Barrier Free Law and Certification System, which reflect these trends. In korean cases, standards such as the size of the doors (width and height), the Unobstructed Manoeuvring Space and Clear Space at the Latch side of the Door are required to improve standards in accordance with international standards. In addition, the expression of laws and evaluation items of BF-Certification should be clearly defined. And the application of visual contrast standards for the enhancement of perceptions presented in international standards should be considered. Implication: Barrier Free related legal standards and evaluation items of BF-Certification that are used in Korea are required to be revised in consideration of social and environmental changes. Comprehensive improvements should be made through detailed review.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.9
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• pp.559-564
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• 2016

This study examined the malfunction mode of the HCMOS IC under narrow-band high-power electromagnetic wave. Magnetron is used to a narrow-band electromagnetic source. MFR (malfunction failure rate) was measured to investigate the HCMOS IC. In addition, we measured the resistance between specific pins of ICs, which are exposed and not exposed to the electromagnetic wave, respectively. As a test result of measurement, malfunction mode is shown in three steps. Flicker mode causing a flicker in LED connected to output pin of IC is dominant in more than 7.96 kV/m electric field. Self-reset mode causing a voltage drop to the input and output of IC during electromagnetic wave radiation is dominant in more than 9.1 kV/m electric field. Power-reset mode making a IC remained malfunction after electromagnetic radiation is dominant in more than 20.89 kV/m. As a measurement result of pin-to-pin resistance of IC, the differences between IC exposed to electromagnetic wave and normal IC were minor. However, the five in two hundred IC show a relatively low resistance. This is considered to be the result of the breakdown of pn junction when latch-up in CMOS occurred. Based on the results, the susceptibility of HCMOS IC can be applied to a basic database to IC protection and impact analysis of narrow-band high-power electromagnetic waves.

• Journal of IKEEE
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• v.23 no.3
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• pp.954-961
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• 2019

This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memory cell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. During the read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable 'low' node close to the ground, thereby improving the dummy-read stability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, the advanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to the commercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designed with an industrial 180-nm low-power CMOS process.

• Journal of Convergence for Information Technology
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• v.11 no.6
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• pp.7-13
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• 2021

In this paper, the function of starting the negative voltage used in the IT equipment when it is generated and the method of controlling it using a microcontroller for the function to detect the overload and respond to it are presented. To do this, the limitations of the existing negative voltage generation circuit and the problems that occur during overload were analyzed, and a circuit that detects and controls the overload condition without a separate current sensing circuit was presented. In order to confirm the effect of the proposed method, an experiment was conducted by configuring an experimental circuit. As a result of the experiment, compared to the existing negative voltage generation circuit, which falls into a latch-up state when overloaded and enters a dangerous state, the proposed circuit detects this, stop the operation of the circuit, and informs the user of such an abnormal state to take action. have. In addition, since the starting point of the circuit is determined according to the system state, the experimental result was confirmed that the starting time was significantly shortened by about 23% compared to the time switch method.