• Title, Summary, Keyword: latch

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The Study of Latch-up (펄스감마선에 의한 DC/DC 컨버터의 Latch-up현상에 대한 연구)

  • Oh, Seung-Chan;Lee, Nam-Ho;Lee, Heung-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.719-721
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    • 2012
  • In this study, we carried out transient radiation experiments for identify failure situation by a transient radiation effect on DC/DC converter device due to high energy ionizing radiation pulse induced to electronic device. This experiments were carried out using a 60 MeV electron beam pulse of the LINAC(Linear Accelerator) facility in the Pohang Accelerator Laboratory. In this experiment, we has found that the latch-up phenomena could be checked in more than $1.0{\times}10^8$rad(si)/sec condition.

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A HDD Latch Design Using Electro-magnetic Force of VCM Actuators (VCM 액추에이터의 전자기력을 이용한 HDD 래치 설계)

  • Kim, Kyung-Ho;Oh, Dong-Ho;Shin, Bu-Hyun;Lee, Seung-Yop
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.19 no.8
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    • pp.788-794
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    • 2009
  • Various types of latch designs for hard disk drives using load/unload mechanism have been introduced to protect undesired release motions of a voice coil motor(VCM) actuator from sudden disturbances. Recently, various inertia-type latches have been widely used because locking performance is better than that of other types of latch. However there has been a limit in the inertia type in order to guarantee perfect latch and unlatch operations because of changes in latch/unlatch conditions due to mechanical tolerance and temperature-dependent friction. In this paper, a reliable and robust magnetic latch mechanism is proposed through only simple modifications of coil and yoke shapes in order to overcome the mechanical limit of current inertia-type latches. This new magnetic latch does not have only a simple structure but it also ensures reliable operations and anti-shock performance. The operating mechanism of the proposed latch is theoretically analyzed and optimally designed using an electromagnetic simulation.

Inertia Latch Design for Micro Optical Disk Drives (초소형 광리스크 드라이브용 관성 래치 설계)

  • 김유성;김경호;유승헌;김수경;이승엽
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.14 no.4
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    • pp.287-294
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    • 2004
  • Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates striction and wear failure modes associated with CSS. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with sin91e spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

Design of Radiation Hardened Shift Register and SEU Measurement and Evaluation using The Proton (내방사선용 Shift Register의 제작 및 양성자를 이용한 SEU 측정 평가)

  • Kang, Geun Hun;Roh, Young Tak;Lee, Hee Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.121-127
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    • 2013
  • Memory devices including SRAM and DRAM are very susceptible to high energy radiation particles in the space. Abnormal operation of the devices is caused by SEE or TID. This paper presents a method to estimate proton SEU cross section representing the susceptibility of the latch circuit that the unit cell of the SRAM and proposes a new latch circuit to mitigate the SEU. 50b shift register was fabricated by using the conventional latch and the proposed latch in $0.35{\mu}m$ process. Irradiation experiment was conducted at KIRAMS by using 43MeV proton beam. It was found that the proposed latch-shift register is not affected by the radiation environment compared to the conventional latch-shift register.

Investigations of Latch-up characteristics of CMOS well structure with STI technology (STI 기술을 채용한 CMOS well 구조에서의 Latch-up 특성 평가)

  • Kim, In-Soo;Kim, Chang-Duk;Kim, Jong-Chul;Kim, Jong-Kwan;Sung, Yung-Kwon
    • Proceedings of the KIEE Conference
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    • pp.339-341
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    • 1997
  • From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

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Characteristics of Latch-up Current of the Dual Gate Emitter Switched Thyristor (Dual Gate Emitter Switched Thyristor의 Latch-up 전류 특성)

  • 이응래;오정근;이형규;주병권;김남수
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.8
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    • pp.799-805
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    • 2004
  • Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

Inertia Latch Design for Micro Optical Disk Drives (초소형 광디스크 드라이브용 관성 래치 설계)

  • 김경호;김유성;이승엽;유승헌;김수경
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • pp.1157-1164
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    • 2003
  • Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates stiction and wear failure modes associated with CSS. Other benefits of L/UL include increased areal density due to smooth disk surfaces, thinner overcoats, and lower head flying height Improved shock resistance due to elimination of head slap, and reduced power consumption. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with single spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

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A Study of CMOS Latch-Up by Layout Dependence (레이아우트 변화에 대한 CMOS의 래치업 특성 연구)

  • 손종형;한백형
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.8
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    • pp.898-907
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    • 1992
  • This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.

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Experimental Analysis and Suppression Method of CMOS Latch-Up Phenomena (CMOS Latch-Up 현상의 실험적 해석 및 그 방지책)

  • Go, Yo-Hwan;Kim, Chung-Gi;Gyeong, Jong-Min
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.5
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    • pp.50-56
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    • 1985
  • A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

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A New SOI LIGBT Structure with Improved Latch-Up Performance

  • Sung, Woong-Je;Lee, Yong-Il;Park, Woo-Beom;Sung, Man-Young
    • Transactions on Electrical and Electronic Materials
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    • v.2 no.4
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    • pp.30-32
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    • 2001
  • In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

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