• Proceedings of the Korean Geotechical Society Conference
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• 2005.10a
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• pp.429-436
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• 2005

In this study, we have compared with the differences between the extent of sampling disturbance and consolidation characteristics by experiments, which are consolidation test and have been performed with Kwang-Yang clay samples. The effects on sampling disturbance to consolidation characteristics of soft clay have been inverstigated by using soil samples obtained from large block sampling and piston sampling methods. Through a few experiments, we've got important results which are that the consoilidation parameter of large block sample(Pc, Cc, Cv) is much larger than the value of parameter of piston sample. We've also found the fact that the large block sample using the large size sampler is much better than piston sample in the quality of goods to lessen the effects on disturbance of sampling. When compared to the parameter of consolidation along with the methods of experiment, we found that the result performed by large size consolidation test is the greatest one and CRS is much better than standard consolidation test to seek for proper parameter.

• Journal of the Korean Geotechnical Society
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• v.23 no.12
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• pp.95-107
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• 2007

This study describes compressive characteristics of marine clay at southwestern coast in Korea by large block and piston samples. Through the analysis of disturbance effect and various consolidation test, consolidation result shows that volumetric strain from large block samples is lower than piston samples and compression index of large block samples is larger than piston samples value. We suggest new empirical equation of compression index by the effect of compression index following sampling method. If consolidation settlement is presumed using empirical equation of compression index, the resort will be more reasonable in predicting settlement than that obtained by the decision of compressibility characteristics from piston samples.

• Journal of Broadcast Engineering
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• v.9 no.1
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• pp.54-63
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• 2004

A new motion compensated frame Interpolation (MCI) algorithm by block based motion estimation (BME) is proposed. The block for the BME is composed of a large overlapped block for practical object motion estimation (ME) and a small block (which has a coinciding center with the ME-block) for the more precise motion compensated image description. Pixels in the block for the ME are sub-sampled to reduce computational complexity. The proposed method is executed with the various ME-blocks which have different size and sub-sampling ratio, and compared to the conventional method.

• Journal of Broadcast Engineering
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• v.25 no.2
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• pp.242-251
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• 2020

Recently, many deep convolutional neural networks for image super-resolution have been studied. Existing deep learning-based super-resolution algorithms are architecture that up-samples the resolution at the end of the network. The post-upsampling architecture has an inefficient structure at large scaling factor result of predicting a lot of information for mapping from low-resolution to high-resolution at once. In this paper, we propose a single image super-resolution using Channel Attention Residual Dense Block based on an iterative up-down sampling architecture. The proposed algorithm efficiently predicts the mapping relationship between low-resolution and high-resolution, and shows up to 0.14dB performance improvement and enhanced subjective image quality compared to the existing algorithm at large scaling factor result.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.230-231
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• 2014

Compressive sensing is a new sampling technique, which allows to sample a signal under the Nyquist-Shannon sampling rate. For block-based compressive sensing, a hybrid sensing matrix which contains low-frequency patterns in addition to the random Gaussian numbers is good for exploiting typical property of natural images. By noting that MH-BCS-SPL is well known for its good recovery performance, this paper investigates effect of the hybrid sensing matrix on MH-BCS-SPL in the sense of how large portion of low-frequency patterns can provide performance improvement.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.661-666
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• 2000

Near-wake flow field of a circular cylinder is studied by means of a cinematic PIV system with high sampling rate and large internal memory block. Experiments are conducted in a closed-cycle water tunnel system and a cross-correlation algorithm in conjunction with FFT (Fast Fourier Transform) analysis and an offset correlation technique is used for vector processing. With the help of very high sampling frequency compared to the shedding frequency, it is possible to obtain phase-averaged information of the three-dimensional wake, even though the shedding is not forced but natural. Phase-locked vortical structures observed simultaneously from the spanwise and cross-stream planes are displayed in the wake-transition regime where fine-scale secondary vortices have a spanwise wavelength or around one diameter. Spatial relations and temporal evolutions of the primary Karman vortex and the secondary vortex are also discussed schematically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.1
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• pp.1-11
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• 2016

We investigate compressive sensing techniques to estimate sparse channel in Orthogonal Frequency Division Multiplexing(OFDM) systems. In the case of large channel delay spread, compressive sensing may not be applicable because it is affected by length of measurement vectors. In this paper, we increase length of measurement vector adding pilot information to OFDM data block. The increased measurement vector improves probability of finding path delay set and Mean Squared Error(MSE) performance. Simulation results show that signal recovery performance of a proposed scheme is better than conventional schemes.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Journal of Korean Society of Forest Science
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• v.35 no.1
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• pp.39-46
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• 1977

In the analysis of variance between population and between individual trees (families), the fluctuation of values of variances due to sample size, (number of family) was analysed by two different designs, i.e. 2-level nested design with equal sample size and randomized complete block design. The variables were seedling heights and root calipers of 1-0 and 1-1 seedlings of Pinus densiflora S. et Z. The details of three natural stands and their progeny characters were presented in previous reports. 1. In nested design analysis. increase of sample size resulted the decrease of F-values among families in general, however, the F-values among populations showen the increasing tendency. The smaller the sample size, the larger the F-values fluctuation was resulted in general. At the point of beyond sample size 10, however, the fluctuation become to be stabilized. The F-value fluctuation seemed to be more in the case of analysis with random sampling method than with sequentially accumulated sampling method. And also such a tendency was more obvious in smaller sample size than in large one. 2. In R.C.B.D. analysis, the sample size to affirm the family variation was smaller than that for population variations.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.