• Smart Media Journal
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• v.6 no.3
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• pp.9-14
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• 2017

This paper is a study on the hardware implementation of the encryption and decryption block of the lightweight block cipher algorithm LEA which can be used for tiny devices in IoT environment. It accepts all secret keys with 128 bit, 192 bit, and 256 bit sizes and aims at the integrated implementation of encryption and decryption functions. It describes design results of applying pipeline method for performance enhancement. When a decryption function is executed, round keys are used in reverse order of encryption function. An efficient hardware implementation method for minimizing performance degradation are suggested. Considering the number of rounds are 24, 28, or 32 times according to the size of secret keys, pipeline of LEA is implemented so that 4 round function operations are executed in each pipeline stage.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.11-18
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• 2007

Multiple linear cryptanalysis has been researched as a method building up the linear attack strength. We indicate that the lastest linear attack algorithm using multiple approximations, which was proposed by Biryukov et al. is hardly applicable to block ciphers with highly nonlinear key schedule, and propose a new multiple linear attack algorithm. Simulation of the new attack algorithm with a small block cipher shows that theory for the new multiple linear cryptanalysis works well in practice.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.4
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• pp.37-44
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• 2008

The 128-bit block cipher SMS4 which is used in WAPI, the Chinese WALN national standard, uses a 128-bit user key with the number of 32 rounds. In this paper, we present a differential attack on the 20-round SMS4 using 16-round differential characteristic. This attack requires $2^{126}$ chosen plaintexts with $2^{105.85}$ 20-round SMS4 decryptions. This result is better than any previously known cryptanalytic results on SMS4 in terms of the numbers of attacked rounds.

• Steel and Composite Structures
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• v.52 no.4
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• pp.435-450
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• 2024

The geometry change of railway tracks significantly influences the safety and ride comfort of high-speed trains. This paper presents an analytical method to map the thermal deformations of a long-span arch bridge to the geometry of CRTS Type I double-block ballastless tracks for high-speed railways. A mechanical model of the bridge-track coupled system was developed to derive analytical formulae of the deformations of the track. The analytical formulae explicitly consider the mechanical properties of the bridge-track coupled system and the temperature profile. A three-dimensional finite element model was established to evaluate the predictions obtained from the analytical formulae. The results show that the analytical formulae provide accurate predictions of the track deformations caused by the thermal deformations of bridges. This research will promote the design, evaluation, and operation of high-speed railway bridges for improved safety and ride comfort in engineering practices.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Journal of the East Asian Society of Dietary Life
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• v.1 no.3
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• pp.305-311
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• 1991

The study was designed to investigate overall acceptability of rice extrudate with added ginseng flour extruded by single screw extruder. Graphic three dimension analysis on response surface regression was conducted for overall acceptability evaluated by balanced incomplete block design. Overall acceptability, which formed a saddle point, increased as moisture content increased at lower die temperature, and as moisture content decreased at higher die temperature. Critical values of each variable which indicated optimum response are 5.0% ginseng content, 17.8% moisture content and 104.6$^{\circ}C$ die temperature, and optimum inferred score of overall acceptability is 59.6 and 90. Key words: extrdate, overall acceptability, response surface regression analysis, balanced incomplete block method.

• Communications for Statistical Applications and Methods
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• v.26 no.6
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• pp.611-622
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• 2019

This paper considers the estimation of the long memory parameter in nonparametric regression with strongly correlated errors. The key idea is to minimize a unified mean squared error of long memory parameter to select both kernel bandwidth and the number of frequencies used in exact local Whittle estimation. A unified mean squared error framework is more natural because it provides both goodness of fit and measure of strong dependence. The block bootstrap is applied to evaluate the mean squared error. Finite sample performance using Monte Carlo simulations shows the closest performance to the oracle. The proposed method outperforms existing methods especially when dependency and sample size increase. The proposed method is also illustreated to the volatility of exchange rate between Korean Won for US dollar.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.2
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• pp.58-63
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• 2010

Cryptography is primarily a computationally intensive process. In this paper we expand AES scheme for analysis of computation time with four criteria, first is the compression of plain data, second is the variable size of block, third is the selectable round, fourth is the selective function of whole routine. We have tested our encryption scheme by c++ using MinGW GCC. Through extensive experimentations of our scheme we found that the optimal block size.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.339-340
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• 2018

본 논문에서는 경량 블록암호 알고리듬 TWINE의 하드웨어 설계에 대해 기술한다. TWINE은 80-비트 또는 128-비트의 마스터키를 사용하여 64-비트의 평문(암호문)을 암호(복호)하여 64-비트의 암호문(평문)을 만드는 대칭키 블록암호이며, s-box와 XOR만 사용하므로 경량 하드웨어 구현에 적합하다는 특징을 갖는다. 암호화 연산과 복호화 연산의 하드웨어 공유를 통해 게이트 수가 최소화 되도록 구현하였으며, 설계된 TWINE 크립토 코어는 RTL 시뮬레이션을 통해 기능을 검증하였다.