• 대한조선학회논문집
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• 제47권3호
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• pp.306-320
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• 2010

Modern ultra-large container carriers can be exposed to the unprecedented springing excitation from ocean waves due to their relatively low torsional rigidity. Large deck opening on the deck of container carriers tends to cause warping distortion of hull structure under wave-induced excitation, eventually leading to the higher chance of resonance vibration between its torsional response and incoming waves. To handle this problem, a higher-order B-spline Rankine panel method and Vlasov-beam FE model was directly coupled in the time domain, and the coupled equation was solved by using an implicit iterative method. In order to capture the complicated behavior of thin-walled open section girder, a sophisticated beam-based finite element model was developed, which takes into account warping distortion and shear-on-wall effect. Then, the developed beam model was directly coupled with the time-domain Rankine panel method for hydrodynamic problem by using the fixed-point iteration method. The developed computational scheme was validated through the comparison with the frequency-domain solution on the container carrier model in linear springing regime.

• 한국군사과학기술학회지
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• 제21권4호
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• pp.437-446
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• 2018

This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

• 한국해양공학회지
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• 제27권4호
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• pp.83-89
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• 2013

A numerical scheme based on a mode superposition method is presented for the dynamic response analysis of a top-tensioned riser (TTR) under sheared current loads. The natural frequencies and mode shapes of the TTR have been calculated analytically for a beam with a slowly varying tension and pinned-pinned boundary conditions at the top and bottom ends. The lift coefficients and corresponding amplitudes used to estimate the vortex-induced modal force and damping for each mode were predicted via iterative calculations based on the input and output power balancing concept. Here, the power-in regions were controlled by the normal distribution function, for which the center was coincident with the lock -in location by local vortex-shedding, and the range was defined by the constant standard deviation for the reduced velocity by the local current speed. Finally, dynamic responses such as root-mean-squared displacement and stress were calculated using the mode superposition technique. In order to verify the presented scheme, a numerical calculation was performed for a TTR under an arbitrary linearly sheared current and linearly varying tension. A comparison with the results of the existing software showed that the presented scheme could give reliable and feasible solutions. Case studies were performed to investigate the effects of various current loads and tensions.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.175-178
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• 2007

3GPP에서는 이동망에서 QoS를 관리하기 위하여 트래픽 조절기가 포함된 QoS 구조에 대해서 정의하고 있다. 본 논문에서는 3GPP에서 정의하는 트래픽 조절기에 적용 가능한 영상 전송 알고리즘을 제안한다. 제안하는 알고리즘은 토큰 버킷을 이용하여 가변적인 트래픽을 제어하는 트래픽 조절기에서 영상의 품질 변화를 최소화 한다. 제안하는 알고리즘은 반복적인 최적화 방법을 사용하지 않고 프레임 레이어에서 전송률을 제어하는 방법으로 영상 프레임간의 왜곡의 변화를 최소화한다. 그리고 전처리가 필요하지 않은 슬라이딩 윈도우 기법을 사용하기 때문에 영상을 압축할 때 추가적인 지연을 발생시키지 않는다. 따라서 제안하는 알고리즘은 낮은 계산량을 필요로 하는 실시간 영상 코덱에 적당한 알고리즘이다.

• 시스템엔지니어링학술지
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• 제1권1호
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• pp.14-19
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• 2005

High temperature vacuum furnaces or high standard electric furnaces demand high technology level and high production cost. Therefore, an iterative design process and the optimization approach under integrated computing environment are required to reduce the development risk. Moreover, it also required to develop an integrated design software that can manage the centralized database system between factory and design department, and the automated furnace design and analysis. The developed software is dedicated to the development of the vacuum (electric) furnaces. Based on the distribute middleware system, the GUI module, the CAD module, the thermal analysis module and the optimization module are integrated. For the DBMS, Microsoft Access is employed, the GUI is developed using Visual Basic language, and AutoCAD is utilized for the configuration design. By investigating the analysis code interface, the analysis and optimization process, and the data communication method, the overall system architecture, the method to integrate the optimizer and ana lysis codes, and the method to manage the data flow are proposed and verified through the optimal furnace design.

• ETRI Journal
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• 제28권5호
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• pp.593-606
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• 2006

Thanks to the great possibilities of providing different types of telecommunication traffic to a large geographical area, satellite networks are expected to be an essential component of the next-generation internet. As a result, issues concerning the designing and testing of efficient connection-admission-control (CAC) strategies in order to increase the quality of service (QoS) for multimedia traffic sources, are attractive and at the cutting edge of research. This paper investigates the potential strengths of a generic digital-video-broadcasting return-channel-via-satellite (DVB-RCS) system architecture, proposing a new CAC algorithm with the aim of efficiently managing real-time multimedia video sources, both with constant and high variable data rate transmission; moreover, the proposed admission strategy is compared with a well-known iterative CAC mainly designed for the managing of real-time bursty traffic sources in order to demonstrate that the new algorithm is also well suited for those traffic sources. Performance analysis shows that, both algorithms guarantee the agreed QoS to real-time bursty connections that are more sensitive to delay jitter; however, our proposed algorithm can also manage interactive real-time multimedia traffic sources in high load and mixed traffic conditions.

• International Journal of Naval Architecture and Ocean Engineering
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• 제7권2호
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• pp.426-434
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• 2015

In this paper we proposed a dada-aided Doppler estimation method for underwater acoustic communication. The training sequence is non-dedicate, hence it can be designed for Doppler estimation as well as channel equalization. We assume the channel has been equalized and consider only flat-fading channel. First, based on the training symbols the theoretical received sequence is composed. Next the least square principle is applied to build the objective function, which minimizes the error between the composed and the actual received signal. Then an iterative approach is applied to solve the least square problem. The proposed approach involves an outer loop and inner loop, which resolve the channel gain and Doppler coefficient, respectively. The theoretical performance bound, i.e. the Cramer-Rao Lower Bound (CRLB) of estimation is also derived. Computer simulations results show that the proposed algorithm achieves the CRLB in medium to high SNR cases.

• Computers and Concrete
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• 제2권5호
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• pp.345-366
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• 2005

This work presents an assessment of the computational performance of a vector-parallel implementation of probabilistic model for concrete cracking in 3D. This paper shows the continuing efforts towards code optimization as reported in earlier works Paz, et al. (2002a,b and 2003). The probabilistic crack approach is based on the direct Monte Carlo method. Cracking is accounted by means of 3D interface elements. This approach considers that all nonlinearities are restricted to interface elements modeling cracks. The heterogeneity governs the overall cracking behavior and related size effects on concrete fracture. Computational kernels in the implementation are the inexact Newton iterative driver to solve the non-linear problem and a preconditioned conjugate gradient (PCG) driver to solve linearized equations, using an element by element (EBE) strategy to compute matrix-vector products. In particular the paper analyzes code behavior using OpenMP directives in parallel vector processors (PVP), such as the CRAY SV1 and CRAY T94. The impact of the memory architecture on code performance, and also some strategies devised to circumvent this issue are addressed by numerical experiment.

• 국제강구조저널
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• 제18권5호
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• pp.1654-1665
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• 2018

In an irregular prism tensegrity, the number of force equilibrium equations is less than the number of unknown parameters of nodal coordinates and member force ratios. As a result, the form-finding process normally becomes nonlinear with additional conditions or needs to be carried out with the use of iterative procedures. For cases of irregular prism tensegrity which involves large number of members, it was found that previously proposed methods of form-finding are not practical. Moreover, there is a need for a form-finding approach which is able to cater to different requirements on final configuration. In this paper, the length relation condition is introduced to be used in combination with the force equilibrium equation. With the combined use of length relation and equilibrium conditions, a linear form-finding approach for irregular prism tensegrity was successfully formulated and developed. An easy-to-use interactive form-finding tool has been developed which can be used for form-finding of irregular prism tensegrities with large number of elements as well as under diverse specific requirements on their configurations.

• 정보보호학회논문지
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• 제12권2호
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.