• Journal of Power Electronics
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• 제13권2호
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• pp.223-231
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• 2013

A modular three-phase multilevel inverter especially suitable for electrical drive applications has been previously presented. This topology is based on series connection of power cells in which each cell comprised of two inverter legs in series. In this paper, in order to generate the maximum number of voltage levels with reduced number of switches, three algorithms are proposed for determination of the magnitudes of dc voltage sources. In addition, a new hybrid multilevel inverter is proposed that is composed of series connection of the previously presented multilevel inverter and some H-bridges. The proposed topology has been compared with some other presented multilevel inverters. The performance of the proposed multilevel inverter has been verified by simulation and experimental results of a single-phase 39-level multilevel inverter.

• Journal of Power Electronics
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• 제16권2호
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1821-1834
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• 2017

Medium voltage control applications due to obtain better output voltage and reduced electro-magnetic interference multi level inverter is used. In closed loop control with inverter, the PI controller does not operate satisfactorily when the operating point changes. This paper presents the performance of Co-Efficient diagram PI controller based indirect vector controlled induction motor drive fed from three-level inverter under different operating conditions (dynamic and steady state). The proposed Co-Efficient diagram PI controller based three level inverter significantly reduces the torque ripple compared to that of conventional PI controller. The performance of the indirect vector controlled induction motor drive has been simulated at different operating conditions. For three-level inverter control, a simplified space vector modulation technique is implemented, which reduces the coordinate transformations complications in the algorithms. The performance parameters, torque ripple contents and THD of induction motor drive with three-level inverter is compared under different operating conditions using CDM-PI and conventional PI controllers.

• 전력전자학회논문지
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• 제10권4호
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• pp.331-338
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• 2005

본 논문에서는 2상 유도전동기의 가변속장치인 2-레그 및 4-레그 2상 인버터의 PWM 방식을 제안하였다. 기존의 SVPWM방식을 2-레그 인버터에 적용하기가 복잡하나, 본 논문에서는 캐리어 삼각파 PWM방식으로 단순화시켰다. 4-레그 인버터의 경우 전압벡터가 16개가 되어 전형적인 공간전압벡터이론을 적용하기가 복잡하다. 따라서, 본 논문에서는 이를 대신하여 2-레그 인버터형 삼각파 PWM방식을 기본으로 하여 4-레그 인버터에 적용할 수 있는 삼각파 PWM파형으로 단순화하였다. 제안된 2상 PWM방식에 대한 타당성을 확인하기 위해 모의 실험과 실험이 실행되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.134-139
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• 2005

This paper presents a cost effective quasi-resonant soft-switching PWM high frequency inverter with minimum circuit components. This inverter can achieve wider soft commutation, simpler power circuit configuration, smaller volumetric size, lower cost and wider power regulation range, higher-efficiency as compared with single ended quasi-resonant ZVS-PFM inverter and active voltage clamped quasi-resonant ZVS-PWM inverter. The operation principle of the proposed inverter is described on the basis of the simulation and experimental results, together with its operating performances in steady state. The operating performances of this unique proposed high frequency inverter based on ZVS and ZCS arms-related soft commutation principle is evaluated and discussed as compared with the active voltage-clamped ZVS-PWM inverter and a conventional single-ended ZVS-PFM inverter. The practical effectiveness of a novel type quasi-resonant soft-switching PWM high frequency inverter using IGBT is actually proved for consumer induction heated appliances as rice cooker, hot water producer, steamer and super heated steamer. The extended bidirectional circuit topology of quasi-resonant PWM high frequency inverter with minimum circuit components is demonstrated, which operate as the direct frequency changer.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• 전기학회논문지
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• 제58권11호
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• pp.2149-2154
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• 2009

Electric power quality in power transmission/distribution systems has considerably been deteriorated with the increase in the capacity of distributed generators (DGs). It is because inverters, connecting DGs to conventional power grids, tend to generate harmonic current and voltage. For harmonic mitigation, a large amount of research has been done on passive and active filters, which have been operating successfully in many countries. This paper, therefore, presents how to adopt the filters to an inverter-based DG, with considering a system consisting of both inverter-based DG and harmonic filters. In particular, this paper describes the simulation results using the PSCAD/EMTDC: firstly, the relationship between total harmonic distortion(THD) of current and output power of DG: secondly, the harmonic mitigation ability of passive and active filters. The system, furthermore, is obliged to satisfy the regulations made by Korean Electric Power Corporation(KEPCO). In the regulations, power factor should be maintained between 0.9 and 1 in a grid-connected mode. Thus, this paper suggests two methods for the system to control its power factor. First, the inverter of DG should control power factor rather than an active filter because it brings dramatic decrease in the capacity of the active filter. Second, DG should absorb reactive power only in the range of low output power in order to prevent useless capacity increase of the inverter. This method is expected to result in the variable power factor of the system according to its output power.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.313-316
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• 2000

This paper proposes a new solution by carrier-based SVPWM method to solve the most serious problem of Flying Capacitor Multi-level Inverter that is unbalance of capacitor voltages The voltage unbalance is occurred by the difference of each capacitor's charging and discharging time applied to Flying Capacitor Multi-level Inverter. It controls the variation of capacitor voltages into the mean'0' during some period by means of new carriers using the leg voltage redundancy in the Inverter. The solution can be easily expanded to the multi-level. Also this method can make the switching loss and conduction loss of device equal by the use of leg voltage redundancy. First the unbalance of capacitor voltage is analyzed and the conventional theory of self-balance using phase-shifted carrier is reviewed. And then the new method that is suitable to the Flying Capacitor Inverter is explained. The simulation results would be shown to verify the proposed method

• Journal of Power Electronics
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• 제16권2호
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• pp.498-511
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• 2016

This paper presents a single-phase five-level inverter controlled by two novel pulse width modulation (PWM) switching techniques. The proposed PWM techniques are designed based on minimum switching power loss and minimum total harmonic distortion (THD). In a single-phase five-level inverter employing six switches, the first proposed PWM technique requires four switches to operate at switching frequency and two other switches to operate at line frequency. The second proposed PWM technique requires only two switches to operate at switching frequency and the rest of the switches to operate at line frequency. Compared with conventional PWM techniques for single-phase five-level inverters, the proposed PWM techniques offer high efficiency and low harmonic components in the output voltage. The validity of the proposed PWM switching techniques in controlling single-phase five-level inverters to regulate load voltage is verified experimentally using a 100 V, 500 W laboratory prototype controlled by dspace 1103.

• Journal of Power Electronics
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• 제12권2호
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• pp.285-293
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• 2012

Multilevel inverters have gained attention in high-power applications due to their numerous advantages in comparison with conventional two-level inverters. In this paper a simplified Space-Vector Modulation (SVM) algorithm for a three-level Neutral-Point Clamped (NPC) inverter is implemented on a Freescale$^{(R)}$ DSP56F8037. The algorithm is based on a simplification of the space-vector diagram for a three-level inverter so that it can be used with a two-level inverter. Once the simplification has been achieved, calculation of the dwell times and the switching sequences are carried out in the same way as for the two-level SVM method. Details of the hardware design are included. Experimental results are analyzed to validate the performance of the simplified algorithm.