• Title/Summary/Keyword: interleaved mode

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DESIGN CONCEPT FOR SINGLE CHIP MOSAIC CCD CONTROLLER

  • HAN WONYONG;JIN Ho;WALKER DAVID D.;CLAYTON MARTIN
    • Journal of The Korean Astronomical Society
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    • v.29 no.spc1
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    • pp.389-390
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    • 1996
  • The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

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Medium Voltage Resonant Converter with Balanced Input Capacitor Voltages and Output Diode Currents

  • Lin, Bor-Ren;Du, Yan-Kang
    • Journal of Power Electronics
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    • v.15 no.2
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    • pp.389-398
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    • 2015
  • This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

Improved DC-DC Bidirectional Converter (개선된 DC-DC 양방향 컨버터)

  • Kim, Seong-Hwan;Hur, Jae-Jung;Jeong, Bum-Dong;Yoon, Kyoung-Kuk
    • Journal of Advanced Marine Engineering and Technology
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    • v.41 no.1
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    • pp.76-82
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    • 2017
  • Since the introduction of electronically controlled engines and electric propulsion ships, the need for an uninterruptible power supply for emergency power supply devices that use batteries has gained importance. The bidirectional converter in such emergency power supply devices is a crucial component. This paper proposes, a topology for an improved DC-DC bidirectional converter that is characterized by a high voltage conversion ratio and low voltage stress of switches. To confirm the performance of the converter, a computer simulation was executed with PSIM software. The conversion ratio of the proposed converter was found to be four times higher than the conventional boost converter in step-up mode and one-fourth that of the conventional buck converter in step-down mode, and the voltage stress of the switches was one-fourth of the high-side voltage. Moreover, the proposed converter was confirmed to be able to distribute equal currents between two interleaved modules without using any extra current-sharing control method because of the charge balance of its blocking capacitors.

Critical Conduction Mode Bridgeless PFC Converter Based on a Digital Control (디지털 제어 기반의 경계점모드 브릿지리스 PFC 컨버터)

  • Kim, Tae-Hun;Lee, Woo-Cheol
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.12
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    • pp.2000-2007
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    • 2016
  • Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

Zero Torque Control of Switched Reluctance Motor for Integral Charging (충전기 겸용 스위치드 릴럭턴스 전동기의 제로토크제어)

  • Rashidi, A.;Namazi, M.M;Saghaian, S.M.;Lee, D.H.;Ahn, J.W.
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.2
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    • pp.328-338
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    • 2017
  • In this paper, a zero torque control scheme adopting current sharing function (CSF) used in integrated Switched Reluctance Motor (SRM) drive with DC battery charger is proposed. The proposed control scheme is able to achieve the keeping position (KP), zero torque (ZT) and power factor correction (PFC) at the same time with a simple novel current sharing function algorithm. The proposed CSF makes the proper reference for each phase windings of SRM to satisfy the total charging current of the battery with zero torque output to hold still position with power factor correction, and the copper loss minimization during of battery charging is also achieved during this process. Based on these, CSFs can be used without any recalculation of the optimal current at every sampling time. In this proposed integrated battery charger system, the cost effective, volume and weight reduction and power enlargement is realized by function multiplexing of the motor winding and asymmetric SR converter. By using the phase winding as large inductors for charging process, and taking the asymmetric SR converter as an interleaved converter with boost mode operation, the EV can be charged effectively and successfully with minimum integral system. In this integral system, there is a position sliding mode controller used to overcome any uncertainty such as mutual inductance or DC offset current sensor. Power factor correction and voltage adaption are obtained with three-phase buck type converter (or current source rectifier) that is cascaded with conventional SRM, one for wide input and output voltage range. The practicability is validated by the simulation and experimental results by using a laboratory 3-hp SRM setup based on TI TMS320F28335 platform.

Dynamic Bandwidth Allocation Scheme with Considering Downstream Traffic in EPON (EPON에서 하향 데이터 전송을 고려한 동적 대역폭 할당 방안)

  • Kim Eun-Chul;Lee Kang-Won;Choi Young-Soo;Cho You-Ze
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.12
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    • pp.37-44
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    • 2005
  • This paper proposes a hybrid scheme for dynamic bandwidth allocation(DBA) in Ethernet passive optical network(EPON), which combines advantages of adaptive cycle and constant cycle-based schemes. The proposed scheme is based on IPACT scheme, but it operates as adaptive cycle or constant cycle mode according to the queue status of optical line terminal(OLT) for downstream transmission. Simulation results showed that the proposed scheme could achieve a similar throughput in downstream transmission to a constant cycle-based DBA scheme, while producing a similar delay performance to the IPACT scheme in upstream transmission.