• Composites Research
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• v.36 no.4
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• pp.270-274
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• 2023

The stacking configuration of fiber-reinforced polymer (FRP) composites, achieved via the filament winding process, exhibits distinct variations compared to conventional FRP composite stacking arrangements. Consequently, it becomes challenging to ascertain the influence of mechanical properties based on the typical stacking structures. Thus, it becomes imperative to enhance the mechanical behavior and optimize the interleaved structures to improve overall performance. Therefore, this study aims to investigate the impact of incorporating amorphous halloysite nanotubes (A-HNTs) within different layers of five unique layer arrangements on the low-velocity impact properties of interleaved carbon fiber-reinforced polymer (CFRP) structures. The low-velocity impact characteristics of the laminate were validated using a drop weight impact test, wherein the resulting impact damage modes and extent of damage were compared and evaluated under microscopic analysis. Each interleaved structure laminate according to whether nanoparticles are added was compared at impact energies of 10 J and 15 J. In the case of 10 J, the absorption energy showed a similar tendency in each structure. However, at 15 J, the absorption energy varies from structure to structure. Among them, a structure in which nanoparticles are not added exhibits the highest absorption energy. Additionally, various impact fracture modes were observed in each structure through optical microscopy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.46-51
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• 2002

A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.6
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• pp.1005-1013
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• 2015

In this paper, an uplink pilot signal structure is proposed for millimeter wave(mmWave)-based mobile wireless backhaul. For the transmit diversity of two antenna ports, uplink pilot signals generated from the Zadoff-Chu sequence can be mapped in an interleaved mode or continuous mode on the frequency axis, and channel estimation algorithms are different depending on the pilot signal mapping schemes. Through a simulation under Rayleigh fading channel assuming a subway scenario, the interleaved mapping scheme showed no performance degradation compared to the continuous mapping scheme and the implementation complexity of the uplink channel estimator was reduced due to the interleaved mapping scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5B
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• pp.457-465
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• 2003

In this paper, we analyze the performances of variable MAC (Medium Access Control) protocols and present an efficient MAC protocol for Ethernet PON (Passive Optical Network). We consider three MAC protocols: static TDMA, dynamic TDMA, and Interleaved polling. Static TDMA assigns an equal amount of bandwidth to all ONUs regardless of the request information but Dynamic TDMA dynamically allocates the bandwidth to each ONU considering its request. Interleaved Polling operates a cycle with variable time period and a polling method for informing a uplink transmission chance to each ONU. This paper theoretically analyzes the available bandwidth for each of three protocols. We also implement the simulation models for them by using OPNET and evaluates the performances under various bursty traffic environments. The results are compared and analyzed in terms of channel utilization and queueing delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.16-24
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• 2009

In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.4
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• pp.298-308
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• 2017

This paper presents a Interleaved Buck Converter(IBC) system with Random PWM to reduce electromagnetic noise by harmonics. Swithced mode power supply generally controlled by high switching frequency have a electromagnetic interference(EMI) issue due to the high-voltage/high-current switching to regulate the voltage in buck converter. To solve the problem. we present a novel IBC system with PRBS. IBC system has two active switches with 180 phase difference that controll the cicuit with two PWM signal. IBC system may be disadventageous for the cost due to the addtion of one set of switch, but it has adventages of power distribution, current ripple cancellation, fast transient response, and passive component size reduction. To verify the validity of study, simulation program has been bulit using PSIM and the experimental results of IBC system using RPWM was compared with the conventinal PWM and randomized PWM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1040-1046
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• 2004

The BLAST-OFDM system is an efficient method for high data rate multimedia transmission in futurewireless communication system. In this paper, a linear preceding mechanism and an efficient antenna-subcarrier assignment algorithm are proposed for the conventional BLAST-OFDM system, in order to utilize the full spatial diversity and the interleaved frequency diversity. By computer simulation, the proposed system has proved to achieve 4-5㏈ gain over the conventional BLAST-OFDM system.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.443-448
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• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.591-595
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• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.