• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.346-349
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• 1988

Conductance technique is the moat accurate method and gives more detailed information about interface of the MIS structure than other methods. With the measurement of the equivalent parallel conductance and capacitance, the characterization of Si-SiN interface is developed. The interface state density of Si-SiN is obtained by $8{\times}10^{11}$ - $6{\times}10^{12}(eV^{-1}cm^{-2}$). After the positive B-T stress is performed on the sample, the interface state density gets increased. The interface state density is not effected by the D.C. stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.10a
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• pp.1-4
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• 1988

The high frequency and quasi-state C-V curves were measured to determine the interface state density in MNOS devices. Berglund method was appropriate for determination of energy distribution of interface state density all over the energy gap. Applying Vg vs Øs relation by Berlund method to comparison-analysis method of the high-frequency and quasi-static C-V curves, we were able to determine the energy distribution by only measured C-V curves without theoretical C-V curves. The interface state density near the conduction band was high at lower temperature than room temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• Korean Journal of Materials Research
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• v.28 no.2
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• pp.118-123
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• 2018

5 nm-thick $SiO_2$ layers formed by plasma-enhanced chemical vapor deposition (PECVD) are densified to improve the electrical and interface properties by using nitric acid oxidation of Si (NAOS) method at a low temperature of $121^{\circ}C$. The physical and electrical properties are clearly investigated according to NAOS times and post-metallization annealing (PMA) at $250^{\circ}C$ for 10 min in 5 vol% hydrogen atmosphere. The leakage current density is significantly decreased about three orders of magnitude from $3.110{\times}10^{-5}A/cm^2$ after NAOS 5 hours with PMA treatment, although the $SiO_2$ layers are not changed. These dramatically decreases of leakage current density are resulted from improvement of the interface properties. Concentration of suboxide species ($Si^{1+}$, $Si^{2+}$ and $Si^{3+}$) in $SiO_x$ transition layers as well as the interface state density ($D_{it}$) in $SiO_2/Si$ interface region are critically decreased about 1/3 and one order of magnitude, respectively. The decrease in leakage current density is attributed to improvement of interface properties though chemical method of NAOS with PMA treatment which can perform the oxidation and remove the OH species and dangling bond.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.189-192
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• 1988

Nitrided oxides have been investigated recently for application as a replacement for thermally grown $SiO_2$ in MIS devices. In this paper, thin oxides were nitrided in $N_2$ Plasma ambient. With the measurement of the equivalent paralled conductance and capacitance by the using coductance technique, the characterization of Si-SiON interface is developed. The interface state density of Si-SiON is obtained by $1{\times}10^{11}{\sim}9{\times}10^{11}(eV^{-1}Cm^{-2})$. After${\pm}$B-T stress is performed on the sample, the interface state density gets increased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.492-499
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• 2013

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (${\Phi}_{bo}$) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The ${\Phi}_{bo}$ and the series resistance ($R_S$) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density ($N_{SS}$) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density $N_{SS}$ as determined by Terman's method is found to be $2.14{\times}10^{12}\;cm^{-2}\;eV^{-1}$ for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.4
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• pp.1095-1101
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• 1995

Numerical analysis of vertical solidification process allowing solid-liquid density change is performed by a hybrid method between a winite volume method (FVM) and a finite element method (FEM). The investigation focuses on the influence of solid-liquid density change and cooling rates on the motion of solid-liquid interface, solidified mass fraction, temperatures and thermal stresses in the solid region. Due to the density change of pure aluminium, solid-liquid interface moves more slowly but the solidified mass fraction is larger. The cooling rate of the wall is shown to have a significant influence on the phase change heat transfer and thermal stresses, while the density change has a small influence on the motion of the interface, solidified mass fraction, temperature distributions and thermal stresses. As the cooling rate increases, the thermal stresses become higher at the early stage of a solidification process, but it has small influence on the final stresses as the steady state is reached.