• Title/Summary/Keyword: interconnection network

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A LDPC Decoder for DVB-S2 Standard Supporting Multiple Code Rates (DVB-S2 기반에서 다양한 부호화 율을 지원하는 LCPC 복호기)

  • Ryu, Hye-Jin;Lee, Jong-Yeol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.118-124
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    • 2008
  • For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization (GPGPU 자원 활용 개선을 위한 블록 지연시간 기반 워프 스케줄링 기법)

  • Thuan, Do Cong;Choi, Yong;Kim, Jong Myon;Kim, Cheol Hong
    • KIPS Transactions on Computer and Communication Systems
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    • v.6 no.5
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    • pp.219-230
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    • 2017
  • General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

Analysis of Technology Association Rules Between CPC Codes of the 'Internet of Things(IoT)' Patent (CPC 코드 기반 사물인터넷(IoT) 특허의 기술 연관성 규칙 분석)

  • Shim, Jaeruen
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.5
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    • pp.493-498
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    • 2019
  • This study deals with the analysis of the technology association rules between CPC codes of the Internet of Things(IoT) patent, the core of the Fourth Industrial Revolution ICT-based technology. The association rules between CPC codes were extracted using R, an open source for data mining. To this end, we analyzed 369 of the 605 patents related to the Internet of Things filed with the Patent Office until July 2019, with a complex CPC code, up to the subclass-level. As a result of the technology association rules, CPC codes with high support were [H04W ${\rightarrow}$ H04L](18.2%), [H04L ${\rightarrow}$ H04W](18.2%), [G06Q ${\rightarrow}$ H04L](17.3%), [H04L ${\rightarrow}$ G06Q](17.3%), [H04W ${\rightarrow}$ G06Q](9.8%), [G06Q ${\rightarrow}$ H04W](9.8%), [G06F ${\rightarrow}$ H04L](7.9%), [H04L ${\rightarrow}$ G06F](7.9%), [G06F ${\rightarrow}$ G06Q](6.2%), [G06Q ${\rightarrow}$ G06F](6.2%). After analyzing the technology interconnection network, the core CPC codes related to technology association rules are G06Q and H04L. The results of this study can be used to predict future patent trends.

Study on the Selecting of Suitable Sites for Integrated Riparian Eco-belts Connecting Dam Floodplains and Riparian Zone - Case Study of Daecheong Reservoir in Geum-river Basin - (댐 홍수터와 수변구역을 연계한 통합형 수변생태벨트 적지 선정방안 연구 - 금강 수계 대청호 사례 연구 -)

  • Bahn, Gwonsoo;Cho, Myeonghyeon;Kang, Jeonkyeong;Kim, Leehyung
    • Journal of Wetlands Research
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    • v.23 no.4
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    • pp.327-341
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    • 2021
  • The riparian eco-belt is an efficient technique that can reduce non-point pollution sources in the basin and improve ecological connectivity and health. In Korea, a legal system for the construction and management of riparian eco-belts is in operation. However, it is currently excluded that rivers and floodplains in dam reservoir that are advantageous for buffer functions such as control of non-point pollutants and ecological habitats. Accordingly, this study presented and analyzed a plan to select a site for an integrated riparian ecol-belt that comprehensively evaluates the water quality and ecosystem characteristics of each dam floodplain and riparian zone for the Daecheong Dam basin in Geum River watershed. First, the Daecheong Dam basin was divided into 138 sub-basin with GIS, and the riparian zone adjacent to the dam floodplain was analyzed. Sixteen evaluation factors related to the ecosystem and water quality impact that affect the selection of integrated riparian eco-belt were decided, and weights for the importance of each factor were set through AHP analysis. The priority of site suitability was derived by conducting an integrated evaluation by applying weights to sub-basin by floodplains and riparian zone factors. In order to determine whether the sites derived through GIS site analysis are sutiable for actual implementation, five sites were inspected according to three factors: land use, pollution sources, and ecological connectivity. As a result, it was confirmed that all sites were appropriate to apply integrated riparian ecol-belt. It is judged that the riparian eco-belt site analysis technique proposed through this study can be applied as a useful tool when establishing an integrated riparian zone management policy in the future. However, it might be necessary to experiment various evaluation factors and weights for each item according to the characteristics and issues of each dam. Additional research need to be conducted on elaborated conservation and restoration strategies considering the Green-Blue Network aspect, evaluation of ecosystem services, and interconnection between related laws and policy and its improvements.