• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.95-96
• /
• 2014

450mm 반도체 CVD 장비 개발 및 300mm F-CVD (Flowable CVD) 공정 개발에 있어서 공정 마진 확보 및 막질 품질 개선을 위해 주파수 가변형 RF Generator가 필수적으로 요구되고 있다. 20nm이하 STI (Shallow Trench Isolation), PMD (Pre-metal Dielectric) & IMD (Inter-Metal Dielectric) 미세공정 gap fill에 많은 문제점이 도출되고 있으며, 이유로는 Generator 고정 주파수에서 Matching Time delay 또는 Shooting에 의한 산포의 한계로 파악되었으며, 주파수 가변에 의한 고속 Tune 기능이 요구되어진다. 따라서 400kHz 주파수 가변형 RF-Generator 개발을 진행하였으며 본 논문을 통해 개발되어진 장비의 성능과 시험 평가한 결과를 소개하고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.544-544
• /
• 2008

Metal-CMP 공정시 높은 압력을 가해 줌으로 인하여 금속배선의 디싱 현상과 에로젼 현상이 발생하고 다공성의 하부층에 균열이 생기는 문제점을 개선하고자, 낮은 하력에서 금속막의 광역 평탄화를 이룰 수 있는 ECMP(Electrochemical Chemical Mechanical Polishing)가 생겨나게 되었다. 본 논문에서는 다양한 전해액의 전류-전압 특성 곡선을 비교 분석하여, 패시베이션막이 형성되는 곳을 알 수 있었고, CV와 LSV 법을 통해 전기화학적인 특성을 고찰하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.185-188
• /
• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2 \; (PN_2)$ gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and $PN_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.63-68
• /
• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.4
• /
• pp.325-331
• /
• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Proceedings of the KIEE Conference
• /
• 2004.07c
• /
• pp.1600-1604
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the KIEE Conference
• /
• 1998.07d
• /
• pp.1327-1329
• /
• 1998

It is very important to select superior inter-layer PMD(Pre Metal Dielectric) materials which can act as penetration barrier to various impurities created by CMP processes. In this paper, hot carrier degradation and device characteristics were studied with material variation of PMD-1 layers, which were split by LP-TEOS, SR-Oxide, PE-Oxynitride, PE-Nitride, PE-TEOS films. It was observed that the oxynitride and nitride using plasma was greatly decreased in hot carrier effect in comparison with silicon oxide. Consequently, silicon oxide turned out to be a better PMD-1 material than PE-oxynitride and PE-nitride. Also, LP-TEOS film was the best PMD-1 material Among the silicon oxides.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.04b
• /
• pp.93-96
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.158-159
• /
• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multilayer interconnection layers. In order to reduce the RC delay, low-k materials will be used for inter-metal dielectric (IMD) materials. We have developed self-consistent simulation tool that includes neutral-species transport model, based on the relaxation continuum (RCT) model. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatiotemporal steady state profile could be obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.389-392
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.