• KIISE Transactions on Computing Practices
• /
• v.20 no.9
• /
• pp.507-512
• /
• 2014

Recently, Distributed computing processing begins using both CPU(Central processing unit) and GPU(Graphic processing unit) to improve the performance to overcome darksilicon problem which cannot use all of the transistors because of the electric power limitation. There is an integrated graphics processor that CPU and GPU share memory and Last level cache(LLC). But, There is no LLC access rules between CPU and GPU, so if GPU and CPU processes run together at the same time, performance of both processes gets worse because of the contention on the LLC. This Paper gives evidence to prove the need of the Cache Partitioning and is mentioned about the cache partitioning design using page coloring to allocate the L3 Cache space only for the GPU process to guarantee GPU process performance.

• Proceedings of the KIEE Conference
• /
• 1990.11a
• /
• pp.443-445
• /
• 1990

In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.85-95
• /
• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Proceedings of the Computational Structural Engineering Institute Conference
• /
• 1995.10a
• /
• pp.215-222
• /
• 1995

The objective of this paper is to develop a finite element structural analysis program using VB(Visual Basic) which has been recently getting popular as development tools of application program for Windows. VB provides several functions to develop an application program easily by supporting event-driven programming method and graphic object as control data type. This system is an integrated processor including preprocessor, solver and postprocessor. Automatic mesh generation is available at preprocess stage, and graphic presentation of deformation and stress is also represented at postprocess one.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.56-70
• /
• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.29 no.1 s.232
• /
• pp.96-106
• /
• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.37-47
• /
• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• Journal of Ship and Ocean Technology
• /
• v.4 no.3
• /
• pp.33-45
• /
• 2000

A computational system for wave and viscous flow analysis (WAVIS) has been developed. The system includes a pre-processor, flow solvers and a post-processor. The pre-processor is composed of full form presentation, surface mesh and field grid generation. The flow solvers are for potential and viscous flow calculation. The post-processor has graphic utility for result analysis. All the programs are integrated in a GUI-launcher package. To validate the developed CFD programs of WAVIS, the calculated results for modern commercial hull forms are compared with measurements. It is found that the results from WAVIS are in good agreement with the experimental data, illustrating the accuracy of the numerical methods employed for WAVIS.

• ETRI Journal
• /
• v.22 no.4
• /
• pp.13-24
• /
• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.345-350
• /
• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.