• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제11권3호
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• pp.1-5
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• 2007

We give an elementary proof of a necessary and sufficient condition for integer translates {${\phi}(t-{\alpha})\;:\;{\alpha}{\in}{\mathbb{Z}}^d$} of ${\phi}$(t) in $L^2({\mathbb{R}}^d)$ to be a frame sequence.

• 대한수학회논문집
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• 제15권2호
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• pp.285-308
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• 2000

We generalize bi-orthogonal (non-orthogona) MRA to frame MRA in which the family of integer translates of a scaling func-tion forms a frame for the initial ladder space V0. We investigate the internal structure of frame MRA and establish the existence of a dual scaling function, and show that, unlike bi-orthogonal MRA, there ex-ists a frame MRA that has no (frame) 'wavelet'. Then we prove the existence of a dual wavelet under the assumption of the existence of a wavelet and present easy sufficient conditions for the existence of a wavelet. Finally we give a new proof of an equivalent condition for the translates of a function in L2(R) to be a frame of its closed linear span.

• 제어로봇시스템학회논문지
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• 제3권2호
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• pp.187-196
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• 1997

This paper presents a semi-automatic methodology to synthesize executable digital controller saftware in a multi-loop control system. A digital controller is described by a task graph and end-to-end timing requirements. A task graph denotes the software structure of the controller, and the end-to-end requirements establish timing relationships between external inputs and outputs. Our approach translates the end-to-end requirements into a set of task attributes such as task periods and deadlines using nonlinear optimization techniques. Such attributes are essential for control engineers to implement control programs and schedule them in a control system with limited resources. In current engineering practice, human programmers manually derive those attributes in an ad hoc manner: they often resort to radical over-sampling to safely guarantee the given timing requirements, and thus render the resultant system poorly utilized. After task-specific attributes are derived, the tasks are scheduled on a single CPU and the compiled kernel is synthesized. We illustrate this process with a non-trivial servo motor control system.