• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of Communications and Networks
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• v.18 no.6
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• pp.892-901
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• 2016

In the multi-user multiple-input multiple-output (MIMO) system, orthogonal random beamforming (ORBF) scheme is proposed to serve multiple users simultaneously in order to achieve the multi-user diversity gain. The opportunistic space-division multiple access system (OSDMA-S) scheme performs multiple weighting matrices during the training phase and chooses the best weighting matrix to be used to broadcast data during the transmitting phase. The OSDMA-S scheme works better than the original ORBF by decreasing the inter-user interference during the transmitting phase. To save more time in the training phase, a partly random multiple weighting matrices selection scheme is proposed in this paper. In our proposed scheme, the Base Station does not need to use several unitary matrices to broadcast pilot symbol. Actually, only one broadcasting operation is needed. Each subscriber generates several virtual equivalent channels with a set of pre-saved unitary matrices and the channel status information gained from the broadcasting operation. The signal-to-interference and noise ratio (SINR) of each beam in each virtual equivalent channel is calculated and fed back to the base station for the weighting matrix selection and multi-user scheduling. According to the theoretical analysis, the proposed scheme relatively expands the transmitting phase and reduces the interactive complexity between the Base Station and subscribers. The asymptotic analysis and the simulation results show that the proposed scheme improves the throughput performance of the multi-user MIMO system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.10
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• pp.1275-1281
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• 2019

The automatic modulation recognition of a radio signal is a major task of an intelligent receiver, with various civilian and military applications. In this paper, we propose a method to recognize the modulation of radio signals in wireless communication based on the deep neural network. We classify the modulation pattern of radio signal by using the LSTM model, which can catch the long-term pattern for the sequential data as the input data of the deep neural network. The amplitude and phase of the modulated signal, the in-phase carrier, and the quadrature-phase carrier are used as input data in the LSTM model. In order to verify the performance of the proposed learning method, we use a large dataset for training and test, including the ten types of modulation signal under various signal-to-noise ratios.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.714-723
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• 2003

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback (CMFB) circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased differential-mode input swing with a proposed error amplifier.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.115-120
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• 2021

In this paper, an operating algorithm for single-phase permanent magnet synchronous motor based on PR current controller is proposed. In general, an asymmetric gap may occur depending on the shape of the rotor of single-phase PMSM, and this causes noise and vibration during high-speed operation. Therefore, in this paper, an operating algorithm for a single-phase PMSM usihng a proportional resonant current conrtoller with excellent control stability was proposed. Proportional resonant current controller has on steady state error is relatevly robust against distortion. Also, steady state error of AC input can be eleminated without complicated calculation process. The validity and availability of the proposed algorithm are verified through the experiment.

• Journal of electromagnetic engineering and science
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• v.7 no.2
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• pp.91-95
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• 2007

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through $0.13{\mu}m$ RF CMOS process for WiBro system. The designed LNA achieves +7.8 dBm of input-referred 3^{rd}$-order intercept point (IIP3) with 13.2 dB of Power Gain, 1.3 dB of noise figure and 5.7mA @1.5V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 dB without degrading other features such as gain and noise figure.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.