• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.59-69
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• 2018

In this paper, we present a robust beamforming design to tackle the weighted sum-rate maximization (WSRM) problem in a multicell multiple-input multiple-output (MIMO) - non-orthogonal multipleaccess (NOMA) downlink system for 5G wireless communications. This work consider the imperfectchannel state information (CSI) at the base station (BS) by adding uncertainties to channel estimation matrices as the worst-case model i.e., singular value uncertainty model (SVUM). With this observation, the WSRM problem is formulated subject to the transmit power constraints at the BS. The objective problem is known as on-deterministic polynomial (NP) problem which is difficult to solve. We propose an robust beam forming design which establishes on majorization minimization (MM) technique to find the optimal transmit beam forming matrix, as well as efficiently solve the objective problem. In addition, we also propose a joint user clustering and power allocation (JUCPA) algorithm in which the best user pair is selected as a cluster to attain a higher sum-rate. Extensive numerical results are provided to show that the proposed robust beamforming design together with the proposed JUCPA algorithm significantly increases the performance in term of sum-rate as compared with the existing NOMA schemes and the conventional orthogonal multiple access (OMA) scheme.