• Title/Summary/Keyword: initialization process

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Design of High Speed Dynamic Latch Comparator with Reduced Offset using Initialization Switch (초기화 스위치를 이용해 오프셋을 감소시킨 고속 다이나믹 래치 비교기 설계)

  • Seong, Kwang-Su;Hyun, Eu-Gin;Seo, Hee-Don
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.10
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    • pp.65-72
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    • 2000
  • In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65${\mu}m$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mV ant 200MHz sampling frequency and the input offset is improved about 80% compared with previous work in $5k{\Omega}$ input resistance.

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The Design of a High-Performance RC4 Cipher Hardware using Clusters (클러스터를 이용한 고성능 RC4 암호화 하드웨어 설계)

  • Lee, Kyu-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.7
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    • pp.875-880
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    • 2019
  • A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

Fast booting solution with embedded linux-based on the smart devices (임베디드 리눅스 기반 단말기의 빠른 부팅 개선 방법)

  • Lee, Gowang-Lo;Bae, Byeong-Min;Park, Ho-Jun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.387-390
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    • 2012
  • In this paper, we propose a fast booting solution with embedded linux-based smart devices. We have divided the fast boot process into six steps, such as boot loader, kernel, file system, the init-scripts, shared libraries, and applications for an embedded linux-based boot process to improve the fast booting. Improvements for the fast boot are made in the boot loader phase, which is the first phase at power-up, and the init-script that runs the boot loader phase. To improve the fast booting, standby time from the boot loader and unnecessary initialization routine have been removed, and uncompressed kernel image loading as well as optimized copy routine have been applied. Further, a technology that replaces binary scripts in init-script phase and light-weight init process have been utilized to improve the boot.

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Presteady State Kinetics of ATP Hydrolysis by Escherichia coli Rho Protein Monitors the Initiation Process

  • Jeong, Yong-Ju;Kim, Dong-Eun
    • Bulletin of the Korean Chemical Society
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    • v.27 no.2
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    • pp.224-230
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    • 2006
  • Escherichia coli transcription termination factor Rho catalyzes the unwinding of RNA/DNA duplex in reactions that are coupled to ATP binding and hydrolysis. We report here the kinetic mechanism of presteady state ATP binding and hydrolysis by the Rho-RNA complex. Presteady state chemical quenched-flow technique under multiple turnover condition was used to probe the kinetics of ATP binding and hydrolysis by the Rho-RNA complex. The quenched-flow presteady state kinetics of ATP hydrolysis studies show that three ATPs are bound to the Rho-RNA complex with a rate of $4.4\;{\times}\;10^5M^{-1}s^{-1}$, which are subsequently hydrolyzed at a rate of $88s^{-1}$ and released during the initiation process. Global fit of the presteady state ATP hydrolysis kinetic data suggests that a rapid-equilibrium binding of ATP to Rho-RNA complex occurs prior to the first turnover and the chemistry step is not reversible. The initial burst of three ATPs hydrolysis was proposed to be involved in the initialization step that accompanies proper complex formation of Rho-RNA. Based on these results a kinetic model for initiation process for Rho-RNA complex was proposed relating the mechanism of ATP binding and hydrolysis by Rho to the structural transitions of Rho-RNA complex to reach the steady state phase, which is implicated during translocation along the RNA.

Application of Weakly Coupled Data Assimilation in Global NWP System (전지구 예보모델의 대기-해양 약한 결합자료동화 활용성에 대한 연구)

  • Yoon, Hyeon-Jin;Park, Hyei-Sun;Kim, Beom-Soo;Park, Jeong-Hyun;Lim, Jeong-Ock;Boo, Kyung-On;Kang, Hyun-Suk
    • Atmosphere
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    • v.29 no.2
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    • pp.219-226
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    • 2019
  • Generally, the weather forecast system has been run using prescribed ocean condition. As it is widely known that coupling between atmosphere and ocean process produces consistent initial condition at all-time scales to improve forecast skill, there are many trials on the application of data assimilation of coupled model. In this study, we implemented a weakly coupled data assimilation (short for WCDA) system in global NWP model with low horizontal resolution for coupled forecast with uncoupled initialization, following WCDA system at the Met Office. The experiment is carried out for a typhoon evolution forecast in 2017. Air-sea exchange process provides SST cooling and gives a substantial impact on tendency of central pressure changes in the decaying phase of the typhoon, except the underestimated central pressure. Coupled data assimilation is a challenging new area, requiring further work, but it would offer the potential for improving air-sea feedback process on NWP timescales and finally contributing forecast accuracy.

Application of chaos theory to simulation output analysis

  • Oh, Hyung-Sool;Lee, Young-Hae
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1994.04a
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    • pp.437-450
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    • 1994
  • The problem of testing for a change in the parameter of a stochastic process is particularly important in simulation studies. In studies of the steady state characteristics of a simulation model, it is important to identify initialization bias and to evaluate efforts to control this problem. A simulation output have the characteristics of chaotic behavior because of sensitive dependence on initial conditions. For that reason, we will apply Lyapunov exponent for diagnosis of chaotic motion to simulation output analysis. This paper proposes two methods for diagnosis of steady state in simulation output. In order to evaluate the performance and effectiveness of these methods using chaos theory, M/M/I(.inf.) queueing model is used for testing point estimator, average bias.

Gene Algorithm of Crowd System of Data Mining

  • Park, Jong-Min
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.40-44
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    • 2012
  • Data mining, which is attracting public attention, is a process of drawing out knowledge from a large mass of data. The key technique in data mining is the ability to maximize the similarity in a group and minimize the similarity between groups. Since grouping in data mining deals with a large mass of data, it lessens the amount of time spent with the source data, and grouping techniques that shrink the quantity of the data form to which the algorithm is subjected are actively used. The current grouping algorithm is highly sensitive to static and reacts to local minima. The number of groups has to be stated depending on the initialization value. In this paper we propose a gene algorithm that automatically decides on the number of grouping algorithms. We will try to find the optimal group of the fittest function, and finally apply it to a data mining problem that deals with a large mass of data.

An Offset Reduction Technique of High Speed Dynamic latch comparator (고속 다이나믹 래치 비교기의 오프셋 최소화 기법)

  • 현유진;성광수;서희돈
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.160-163
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    • 2000
  • In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.

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Nonlinear Bearing Only Target Tracking Filter (방위각 정보만을 이용한 비선형 표적추적필터)

  • Yoon, Jangho
    • Journal of Aerospace System Engineering
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    • v.10 no.1
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    • pp.8-14
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    • 2016
  • The optimal estimation of a bearing only target tracking problem be achieved through the solution of the Fokker-Planck equation and the Bayesian update. Recently, a nonlinear filtering algorithm using a direct quadrature method of moments in which the associated Fokker-Planck equation can be propagated efficiently and accurately was proposed. Although this approach has demonstrated its promising in the field of nonlinear filtering in several examples, the "degeneracy" phenomenon, similar to that which exists in a typical particle filter, occasionally appears because only the weights are updated in the modified Bayesian rule in this algorithm. Therefore, in this paper to enhance the performance, a more stable measurement update process based upon the update equation in the Extended Kalman filters and a more accurate initialization and re-sampling strategy for weight and abscissas are proposed. Simulations are used to show the effectiveness of the proposed filter and the obtained results are promising.

Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA (블록 암호 ARIA를 위한 고속 암호기/복호기 설계)

  • Ha, Seong-Ju;Lee, Chong-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.9
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    • pp.1652-1659
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    • 2008
  • With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.