• Title/Summary/Keyword: in-situ post annealing

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Thermal treatment dependences of MFS devices in $BaMgF_4$ thin films on silicon structures ($BaMgF_4$ 박막을 이용한 MFS 디바이스의 열처리 의존성)

  • 김채규;정순원;이상우;김광호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.06a
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    • pp.59-62
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    • 1998
  • Thermal treatment dependences of MFS devices in $BaMgF_4$ on Si structures have been investigated. $BaMgF_4$ thin films have been directly deposited on the p-Si(100) wafers at a low temperature of $300^{\circ}$ in an ultra high vacuum(UHV) system. After in-situ post-deposition annealing was conducted for 20 s at $650^{\circ}$, bias and temperature were applied to $BaMgF_4/Si$ structures. Although X-ray diffraction analysis showed that the films were polycrystalline in nature before and after bias temperature, the C-V properties were some different between with and without bias-temperature treatment.

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Photoluminescence properties of N-doped and nominally undoped p-type ZnO thin films

  • Jin, Hu-Jie;Jeong, Yun-Hwan;Park, Choon-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.04a
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    • pp.65-66
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    • 2008
  • The realization and origin of p-type ZnO are main issue for photoelectronic devices based on ZnO material. N-doped and nominally undoped p-type ZnO films were achieved on silicon (100) and homo-buffer layers by RF magnetron sputtering and post in-situ annealing. The undoped film shows high hole mobility of 1201 $cm^2V^{-1}s^{-1}$ and low resistivity of $0.0454\Omega{\cdot}cm$ with hole concentration of $1.145\times10^{17}cm^{-3}$. The photoluminescence(PL) spectra show the emissions related to FE, DAP and defects of $V_{Zn}$, $V_O$, $Zn_O$, $O_i$ and $O_{Zn}$.

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Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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Fabrication and Properties of MFSFET′s Using $BaMgF_4$/Si Structures for Non-volatile Memory ($BaMgF_4$/Si 구조를 이용한 비휘발성 메모리용 MFSFET의 제작 및 특성)

  • 이상우;김광호
    • Electrical & Electronic Materials
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    • v.10 no.10
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    • pp.1029-1033
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    • 1997
  • A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

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Effects of High-temperature Annealing of CeO$_2$ Buffer Layers on the Surface Morphology of YBa$_2Cu_3O_{7-{\delta}}$ Films on CeO$_2$-buffered R-cut Sapphire Substrates (CeO$_2$ 완충층에 대한 고온 열처리가 CeO$_2$ 완충층을 지닌 R-cut 사파이어 기판 우에 성장된 YBa$_2Cu_3O_{7-{\delta}}$ 박막의 표면상태에 미치는 영향)

  • Lee, Jae-Hun;Yang, Woo-Il;Jang, Jeong-Mun;Ryu, Jae-Su;Komashko, V.A.;Lee, Sang-Yeong
    • 한국초전도학회:학술대회논문집
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    • v.9
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    • pp.152-159
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    • 1999
  • YBa$_2Cu_3O_{7-{\delta}}$ (YBCO) films grown on CeO$_2$-buffered r-cut sapphire substrates (CbS's) were prepared and their structural and electrical properties were measured. Post-annealed CeO$_2$ films were used as buffer layers for the experiments. It turned out that the YBCO films grown on post-annealed CbS's had the rms roughness of less than 20 ${\AA}$ and peak-to-peak roughness of about 30 ${\AA}$ when the YBCO film thickness was 3000 ${\AA}$. Meanwhile, YBCO films on in-situ grown CeO$_2$ buffer layers on r-cut sapphire substrates appeared to have the peak-to-peak roughness of more than 450 ${\AA}$. X-ray diffraction data revealed that the YBCO flms were epitaxially grown along the c-axis with the typical FWHM of(005) ${\theta}$ -2 ${\theta}$ peak about 0. 16 $^{\circ}$ and ${\Delta}$ ${\omega}$ of the (005) peak about 0.5 $^{\circ}$. T$_c$ > 87 K, ${\Delta}$T < 1 K and R(look)/R(100K) ${\ge}$3 were observed from the YBCO films. Applicability of the YBCO films for high-frequency applications was described.

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Change of Schottky barrier height in Er-silicide/p-silicon junction (어븀-실리사이드/p-형 실리콘 접합에서 쇼트키 장벽 높이 변화)

  • Lee, Sol;Jeon, Seung-Ho;Ko, Chang-Hun;Han, Moon-Sup;Jang, Moon-Gyu;Lee, Seong-Jae;Park, Kyoung-Wan
    • Journal of the Korean Vacuum Society
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    • v.16 no.3
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    • pp.197-204
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    • 2007
  • Ultra thin Er-silicide layers formed by Er deposition on the clean p-silicon and in situ post annealing technique were investigated with respect to change of the Schottky barrier height. The formation of Er silicides was confirmed by XPS results. UPS measurements revealed that the workfunction of the silicide decreased and was saturated as the deposited Er thickness increased up to $10{\AA}$. We found that the silicides were mainly composed of Er5Si3 phase through the XRD experiments. After Schottky diodes were fabricated with the Er silicide/p-Si junctions, the Schottky barrier heights were calculated $0.44{\sim}0.78eV$ from the I-V measurements of the Schottky diodes. There was large discrepancy in the Schottky barrier heights deduced from the UPS with the ideal junction condition and the real I-V measurements, so that we attributed the discrepancy to the $Er_5Si_3$ phase in the Er-silicides and the large interfacial density of trap state of it.