• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.43-53
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• 1994

With remarkable progress of hardware technologies, multiprocessor systems equipped with thousands of processors will be available in near future. In order to increase the performance of these systems, many processor allocation algorithms have been proposed. However, few studies have been conducted in order to compare the performance of these algorithms. In this paper, simulation techniques are used in order to compare the performance of the processor allocation algorithms proved to be useful. These are: an algorithm using equipartion, an algorithm using average parallelism, an algorithm using execution signatures, and an algorithm using the number of tasks in a task precedence graph. Simulation shows that the algorithm using execution signatures performs best while the algorithm using average parallelism performs worst with small allocated processors. Surprisingly, the algorithm using equipartition performs well despite the fact that it has smallest overhead. Overall, it can be recommended that the algorithm using equipartition be used without any execution history and that the algorithm using execution signatures be used with some execution history.

• Journal of Korea Multimedia Society
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• v.16 no.2
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• pp.198-205
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• 2013

In this paper, the performance of multicore processor architecture is analyzed which utilizes out-of-order superscalar processor core using multiple basic block execution. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the out-of-order superscalar processor with the window size from 32 to 64 and the number of cores between 1 and 16, exploiting multiple basic block execution from 1 to 4 extensively. As a result, the multicore out-of-order superscalar processor with 4 basic block execution achieves 22.0 % average performance increase over the same architecture with the single basic block execution.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.1
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• pp.87-99
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• 1999

A shop floor control system(SFCS) performs the production activities required to fill orders. In order to effectively control these activities, the autonomous agent-based heterarchical shop floor control architecture is adopted where a supervisor does not exist. In this paper, we define functional perspective of the heterarchical shop floor control using planning, scheduling, and execution modules. In particular, we focus on an execution module that can coordinate the planning and scheduling modules and a general execution module that easily can be modified to execute the other equipment. The execution module can be defined informally as a module that downloads and performs a set of scheduled tasks. The execution module is also responsible for identifying and resolving various errors whether they come from hardware or software. The purpose of this research is to identify all the execution activities and solving techniques under the assumptions of the heterarchical control architecture. And we model the execution module in object-oriented modelling technique for generalization. The execution module modeled in object-oriented concept can be adopted to the other execution module easily. This paper also proposes a classification scheme for execution activities of the heterarchical control architecture. Petri-nets are used as a unified framework for modeling and controlling execution activities. For solving the nonexistence of a supervisor, a negotiation-based solution technique is utilized.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.51-60
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• 2016

Embedded software has requirements such as real-time and environment independency. The real-time requirement is affected from worst-case execution time of loaded tasks. Therefore, to guarantee real-time requirement, we need to determine a program's worst-case execution time using static analysis approach. However, the existing methods for worst-case execution time analysis do not consider the environment independency. Thus, in this paper, in order to provide environment independency, we propose a method for measuring task's execution time from the source codes. The proposed method measures the execution time through the control flow graph created from the source codes instead of the executable codes. However, the control flow graph created from the source code does not have information about execution time. Therefore, in order to provide this information, the proposed method identifies the relationships between statements in the source code and instructions in the executable code. By parameterizing those parts that are dependent on processors based on the relationships, it is possible to enhance the flexibility of the tool that measures the worst-case execution time.

• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.163-170
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• 2008

Due to the proliferation of the Internet and intranet, a new application domain called stream data processing has emerged. Stream data is real-timely and continuously generated. In this paper, we focus on the processing of stream data whose characteristics vary unpredictably by over time. Particularly, we suggest a method which generates an efficient operator execution order called WT-Heuristics. WT-Heuristics efficiently determines the operator execution order since it considers only two adjacent operators in the operator execution order. Also, our method changes the execution order with respect to the change of data characteristics with minimum overheads.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.34 no.1
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• pp.14-24
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• 2011

Though many researchers have interested in the effects of creativity management on the business performance, few have researched the relationship between management execution systems for creativity management and the performance. This paper tried to identify the relationship between management execution systems for creativity management and the performance by using 181 Korean companies' survey data. In this paper, a creative management execution system is modelled by the six criteria that are widely used in the Malcolmn Baldrige National Quality Award, and the performance is measured by a composite variable called by business capability. Through an analysis of survey data using factor analysis and regression analysis, this paper tried to answer two research questions: Firstly, does creative management execution systems have the characteristics of multi-dimensionality? Secondly, does creative management execution systems have an impact on the firm's performance? It was found that a creative management execution system largely consists of two parts, which are called 'system factor' and 'management support factor', and system factors have a more strong impact on the performance. The contribution of this paper is in suggesting that establishing a systematic creative management execution system is required in order to efficiently manage for creativity.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.193-200
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• 1995

A shop floor control system(SFCS), a central part of agile manufacturing, performs the production activities required to fill orders. In order to effectively control these activities, CSCW (computer supported cooperative work) is adopted where a supervisor does not exist. In this paper, we define functional perspective of CSCW-based shop floor control using planning, scheduling, and execution functions. In particular, we focus on an execution model that can coordinate the planning and scheduling functions. Execution can be defined informally as a function that downloads and performs a set of scheduled tasks. Execution is also responsible for identifying and resolving various errors whether they come from hardware or software. The purpose of this research is to identify all the execution activities and solving techniques under the assumptions of CSCW-based heterarchical control architecture. This paper also proposes a classification scheme for execution activities of CSCW-based heterarchical control architecture. Petri-nets are used as a unified framework for modeling and controlling execution activities. For solving the nonexistence of a supervisor, A negotiation-based solution technique is utilized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.143-149
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• 2020

Currently, a multi-core processor is mainly used as a central processing unit of a computer system, and a high-performance out-of-order processor is adopted as each core to maximize system performance. The early out-of-order execution processor with Tomasulo algorithm aimed at floating-point instructions, and it took several cycles to execute by the use of complex structures such as reorder buffer and reservation station. However, in order for the processor to properly utilize out-of-order execution and increase the throughput of instructions, it must operate in a fully pipelined manner. In this paper, a fully pipelined out-of-order processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, a program composed of ARM instructions is successfully performed.