• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.508-519
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• 2007

Flash memory based storage has been used in various mobile systems and now is to be used in Laptop computers in the name of Solid State Disk. The Flash memory has not only merits in terms of weight, shock resistance, and power consumption but also limitations like erase-before-write property. To overcome these limitations, Flash memory based storage requires special address mapping software called FTL(Flash-memory Translation Layer), which often performs merge operation for block recycling. In order to reduce block recycling cost in NAND Flash memory based storage, we introduce another block recycling scheme which we call migration. As a result, the FTL can select either merge or migration depending on their costs for each block recycling. Experimental results with Postmark benchmark and embedded system workload show that this cost-based selection of migration/merge operation improves the performance of Flash memory based storage. Also, we present a solution of macroscopic optimal migration/merge sequence that minimizes a block recycling cost for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be more improved by the macroscopic optimization than the simple cost-based selection.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.590-597
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• 2002

Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.141-145
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• 2021

Various types of memory architectures have been developed, and various compiler optimization techniques have been studied to efficiently use them. In particular, since a memory is a major component that determines performance in mobile computing devices, various optimization techniques have been developed to support them. Recently, a lot of research on hybrid type memory architecture is being conducted, so various compiler techniques are being studied to support it. Existing compiler optimization techniques can be used to achieve the required minimum performance and constraint on low power according to market requirements. References for determining the low-power effect and the degree of performance improvement using these optimization techniques are not properly provided yet. This study was conducted to provide the experimental results of the existing compiler technique as a reference for the development of multibank memory architecture.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Journal of KIISE:Databases
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• v.37 no.5
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• pp.238-249
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• 2010

Flash memory has been studied as a storage medium in order to improve the performance of the system using its high computing speed in the DBMS field where frequent data access is needed. The most difficulty using the flash memory is the performance degradation and the life span shortening of flash memory coming from inefficient in-place update. Log based approaches have been studied to solve inefficient in-place update problem in the DBMS where write operations occur in smaller size of data than page frequently. However the existing log based approaches suffer from the frequent merging operations, which are the principal cause of performance deterioration. Thus is because their fixed log area management can not guarantee a sufficient space for logs. In this paper, we propose non-fixed log area management technique that can minimize the occurrence of the merging operations by promising an enough space for logs. We also suggest the cost calculation model of the optimal log sector number minimizing the system operation cost in a block. In experiment, we show that our non-fixed log area management technique can have the improved performance compared to existing approaches.

• KIISE Transactions on Computing Practices
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• v.22 no.10
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• pp.513-520
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• 2016

As IoT devices become more common in the public sphere, the energy efficiency of embedded systems becomes a problem of major interest in addition to the system performance. Energy efficiency is important for portable embedded systems because they obtain power from their battery, and a low energy efficiency will result in a low usage time while a high energy efficiency will allow for longer usage time. In this paper, we propose a memory usage based frequency selection method to improve the energy efficiency of embedded Linux systems by using devfreq to select the device's system frequency. In our experiments, we found that the proposed method reduces energy consumption in an embedded device by up to 18%.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.1
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• pp.86-98
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• 2019

Recently, the trend of building container-based PaaS (Platform-as-a-Service) is expanding. Container-based platform technology has been a core technology for realizing a PaaS. Containers have lower operating overhead than virtual machines, so hundreds or thousands of containers can be run on a single physical machine. However, recording and monitoring the storage logs for a large number of containers running in cloud computing environment occurs significant overhead. This work has identified two problems that occur when detecting a file system change event of a container running in a cloud computing environment. This work also proposes a system for container file system event detection in the environment by solving the problem. In the performance evaluation, this work performed three experiments on the performance of the proposed system. It has been experimentally proved that the proposed monitoring system has only a very small effect on the CPU, memory read and write, and disk read and write speeds of the container.

• Journal of Korean Society for Geospatial Information Science
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• v.25 no.1
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• pp.29-36
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• 2017

In this paper, we implement a spatial big data analysis prototype based on Spark which is an in-memory system and compares the performance by the spatial split algorithm on this basis. In cluster computing environments, big data is divided into blocks of a certain size order to balance the computing load of big data. Existing research showed that in the case of the Hadoop based spatial big data system, the split method by spatial is more effective than the general sequential split method. Hadoop based spatial data system stores raw data as it is in spatial-divided blocks. However, in the proposed Spark-based spatial analysis system, there is a difference that spatial data is converted into a memory data structure and stored in a spatial block for search efficiency. Therefore, in this paper, we propose an in-memory spatial big data prototype and a spatial split block storage method. Also, we compare the performance of existing spatial split algorithms in the proposed prototype. We presented an appropriate spatial split strategy with the Spark based big data system. In the experiment, we compared the query execution time of the spatial split algorithm, and confirmed that the BSP algorithm shows the best performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.151-156
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• 2012

When mounting the sensor device in the way of Plug&Play, sensor device drivers need to be loaded and linked dynamically. Since a sensor node platform is based on small 8 bit MCU, dynamic loading and linking technique used in Windows and Linux can not be applied. In this paper, we present how to link and load dynamically sensor device drivers for sensor device Plug&Play. We implement a prototype and evaluate it to make sure that there is no performance degradation like sensor device driver connection speed and memory usage. Connection speed overhead increases to 0.2ms. Memory usage overhead increases to hundreds byte. It shows that there is no heavy influence in running the actual program.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.