• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.28B no.5
• /
• pp.327-334
• /
• 1991

This paper proposes an efficient method of implementing the generalized Hough transform (GHT), which has been hindered by an excessive computing load and a large memory requirement. The conventional algorithm requires a parameter space of 4 dimensions in detection a rotated, scaled, and translated object in an input image. Prior to the application of GHT to the input image, the proposed method determines the angle of rotation and the scaling factor of the test image using the proportion of the edge components between the reference image and test image. With the rotation angle and the scaling factor already determined, the parameter spaceis to be reduced to a simple array of 2 dimensions by applying the unit GHT only one time. The experiments with the image of airplanes reveal that both of the computing time and the requires memory size are reduced by 95 percent, without any degradatationof accuracy, compared with the conventional GHT algorithm.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.4
• /
• pp.270-274
• /
• 2009

In this paper, we propose an efficient computation method over GF($2^m$) for memory-constrained devices. While previous methods concentrated only on fast multiplication, we propose to reduce the amount of required memory by cleverly changing the order of suboperations. According to our experiments, the new method reduces the memory consumption by about 20% compared to the previous methods, and it achieves a comparable speed with them.

• Journal of the Korea Society of Computer and Information
• /
• v.26 no.4
• /
• pp.113-118
• /
• 2021

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Journal of Information Technology Applications and Management
• /
• v.13 no.2
• /
• pp.115-126
• /
• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.4
• /
• pp.274-282
• /
• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.267-269
• /
• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes.

• Journal of Information Technology Applications and Management
• /
• v.13 no.4
• /
• pp.257-271
• /
• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes. Based on the results of the performance evaluation, we conclude that F-Tree indexing scheme outperforms the traditional indexing scheme.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.2
• /
• pp.177-185
• /
• 2010

Ray-object intersection is an important element in ray tracing that takes up a substantial amount of computing time. In general, such spatial data structure as kd-tree has been frequently used for static scenes to accelerate the intersection computation. Recently, a few variants of kd-tree traversal have been proposed suitable for the GPU that has a relatively restricted computing architecture compared to the CPU. In this article, we propose yet another two implementation techniques that can improve those previous ones. First, we present a cached stack method that is aimed to reduce the costly global memory access time needed when the stack is allocated to global memory. Secondly, we present a rope-with-short-stack method that eases the substantial memory requirement, often necessary for the previous rope method. In order to show the effectiveness of our techniques, we compare their performances with those of the previous GPU traversal methods. The experimental results will provide prospective GPU ray tracer developers with valuable information, helping them choose a proper kd-tree traversal method.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.4
• /
• pp.305-311
• /
• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• KIISE Transactions on Computing Practices
• /
• v.23 no.7
• /
• pp.428-433
• /
• 2017

Recently, the demand for high performance non-volatile memory storage devices that can replace existing hard disks has been increasing in environments requiring high performance computing such as data-centers and social network services. The performance of such non-volatile memory can greatly depend on the interface between the host and the storage device. With the evolution of storage interfaces, the non-volatile memory express (NVMe) interface has emerged, which can replace serial attached SCSI and serial ATA (SAS/SATA) interfaces based on existing hard disks. The NVMe interface has a higher level of scalability and provides lower latency than traditional interfaces. In this paper, an evaluation and analysis are conducted of the performance of NVMe storage devices through various workloads. We also compare and evaluate the cost efficiency of NVMe SSD and SATA SSD.