• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.131-136
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• 1990

In this paper, new methods are proposed which speed up the logical redundancy identification for the gate-level logic optimization. Redundancy indentification, as well as deterministic test pattern generation, can be viewed as a finite space search problem, of which execution time depends on the size of the search space. For the purpose of efficient search, we propose dynamic head line and mandatory assignment. Dynamic head lines are changed dynamically in the process of the redundancy identification. Mandatory assignement can avoid unnecessary assignment. They can reduce the search size efficiently. Especially they can be used even though the circuit is modified in the optimization procedure, that is different from the test pattern generation methods. Some experimental results are presented indicating that the proposed methods are faster than existing methods.

• Progress in Superconductivity and Cryogenics
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• v.6 no.4
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• pp.37-40
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• 2004

A 1 MV A single phase high temperature superconducting (HTS) transformer was manufactured and tested. The rated voltages of primary and secondary of the HTS transformer are 22.9 kV and 6.6 kV respectively. BSCCO-2223 HTS tape was used for HTS windings of 1 MV A HTS transformer. In order to reduce AC loss generated in the HTS winding, the type of concentric arrangement winding was adopted to a 1 MV A HTS transformer. Single HTS tape for primary windings and 4 parallel HTS tapes for secondary windings were used considering the each rated current of the HTS transformer. A core of HTS transformer was fabricated as a shell type core made of laminated silicon steel plate. And a GFRP cryostat with a room temperature bore was also manufactured. The characteristic tests of 1 MV A HTS transformer were performed such as no load test, short circuit test and several insulation tests at 65 K using sub-cooled liquid nitrogen. From the results of tests, the validity of design of HTS transformer was ascertained.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.803-807
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• 2008

A making process of DSC(dye sensitized solar cell) was presented. In general, Photo electrodes of DSC was made by using colloid paste of nano $TiO_2$ and processing of Doctor-blade printing and high temperature sintering for porous structure. These methods lead to cracks on $TiO_2$ surface and ununiform of $TiO_2$ thickness. This phenomenon is one factor that makes low efficiency to cells. After $TiO_2$ printing on TCO glass, a physical vibration was adapted for reducing ununiform of $TiO_2$ thickness. And a thermal treatment at low temperature(under $75^{\circ}C$) was adapted for reducing cracks on $TiO_2$ surface. In this paper, we have designed and manufactured an ultrasonic circuit (100W, frequency and duty variable) and a thermal equipment. Then, we have optimized forcing time, frequency and duty of ultrasonic irradiation and thermal heating for surface treatment of photo-electrode of DSC. In I-V characteristic test of DSC, ultrasonic and thermal treated DSC shows 19% improved its efficiency against monolithic DSC. And it shows stability of light-harvesting from drastically change of light irradiation test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.2
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• pp.261-271
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• 1997

This paper presents the design process and characteristic test results of tension sensors for measuring the ultimate tension forces of surgical wires. Three types of sensor were designed and tested for calibration. The first two types which transfer the wire tension to the sensing element by direct contact have too much hysterisis errors due to the firctional effect. This error can be considerably reduced in the modified structure, where a cover and a loading button is used to transfer force and moment to the sensing element. The strains predicted by theoretical equations agree well with those by finite element calculations neglecting friction and the strains by finite element analysis considering friction are in good agreement with those measured by four strain gages. The modified ring type tension sensor developed in this paper is expected to be useful for measuring the tension of surgical wires with nonlinearity of 1.31%FS, hysterisis of 5.74%FS and repeatability of 0.19%FS.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.603-609
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• 2008

Nowadays, double-system of TFM(Track-side Functional Modules) developed instead of single-system in use of high speed line to acquisition more availability. Safety Law for Railroad recommend to quality certification of development and general railway machines. It is important to select metrics which form the bases for testing software products. A number of package software development part do not open source cords, so testing external characteristic vectors having relationship with metrics. In this paper, review the process for the TFM Point Modules, Universal Modules and Switchers, think about the test methode of circuit boards output performance by using TFM tester and Simulators.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.237-240
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• 2005

This paper propose an novel CAVLC architcture for H.264 and designed the CAVLC module which can be used in AMBA based design. This designed module can be operated in 420 cycle for one-macroblock and support both long-start code method using Annex B.1 and RTP. To verify the CAVLC architecture, we developed the reference C from JM8.5 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 54MHz clock system, and has 14096 gate counts using Hynix 0.35 um TLM process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.