• Title/Summary/Keyword: in-circuit test

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A Study on the ESD Effect and Measurement for PCB (PCB 선로의 ESD 영향 및 측정법에 관한 연구)

  • Lee, Kwan-Hun;Hwang, Soon-Mi;Song, Byoung-Suk
    • Journal of Applied Reliability
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    • v.11 no.3
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    • pp.245-249
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    • 2011
  • Through the test of ESD(Electro Static Discharge) for PCB circuit, we are able to research on the ESD effect. This paper also studys on the ESD test method for measurement. In the measurement of the discharge current, we used current probe(TC-1). The applied voltage to the PCB metal is -3 kV HBM mode. In conclusion ESD influences exponentially greater impact in nearer PCB circuit.

The PLD Circuit Design of Pattern Generator for the Logical Inspection of Logical Defection (논리결함 검사를 위한 Pattern Generator의 PLD 회로 설계)

  • 김준식;노영동
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.4
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    • pp.1-7
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    • 2003
  • In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

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A Fault Simulation Method Based on Primary Output (근본 출력에 근거한 고장 모의실험)

  • 이상설;박규호
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.6
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    • pp.63-70
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    • 1994
  • In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.

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Flux residue effect on the electrochemical migration of Sn-3.0Ag-0.5Cu (Sn-3.0Ag-0.5Cu 솔더링에서 플럭스 잔사가 전기화학적 마이그레이션에 미치는 영향)

  • Bang, Jung-Hwan;Lee, Chang-Woo
    • Journal of Welding and Joining
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    • v.29 no.5
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    • pp.95-98
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    • 2011
  • Recently, there is a growing tendency that fine-pitch electronic devices are increased due to higher density and very large scale integration. Finer pitch printed circuit board(PCB) is to be decrease insulation resistance between circuit patterns and electrical components, which will induce to electrical short in electronic circuit by electrochemical migration when it exposes to long term in high temperature and high humidity. In this research, the effect of soldering flux acting as an electrical carrier between conductors on electrochemical migration was investigated. The PCB pad was coated with OSP finish. Sn3.0Ag0.5Cu solder paste was printed on the PCB circuit and then the coupon was treated by reflow process. Thereby, specimen for ion migration test was fabricated. Electrochemical migration test was conducted under the condition of DC 48 V, $85^{\circ}C$, and 85 % relative humidity. Their life time could be increased about 22% by means of removal of flux. The fundamentals and mechanism of electrochemical migration was discussed depending on the existence of flux residues after reflow process.

Curriculum for Basic Digital Logic Circuit Practices through Arduino Device Programming (아두이노 장치 프로그래밍을 통한 기초 디지털 논리 회로 실습 교육 과정)

  • Hur, Kyeong
    • Journal of Practical Engineering Education
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    • v.9 no.1
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    • pp.41-48
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    • 2017
  • In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

Design of an Integrated Circuit for Controlling the Printer Head Ink Nozzle (프린터 헤드 노즐분사 제어용 집적회로설계)

  • 정승민;김정태;이문기
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.4
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    • pp.798-804
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    • 2003
  • In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

Fault diagnosis of logical circuit by use of correlation and neural network

  • Kashiwagi, Hiroshi;Sakata, Masato
    • 제어로봇시스템학회:학술대회논문집
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    • 1992.10b
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    • pp.569-572
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    • 1992
  • This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.

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Implementation of multiple valued squential circuit using decision diagram (결정도에 의한 다치 순차회로 구현)

  • 김성대;김휘진;박춘명;송홍복
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.278-281
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    • 1999
  • In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

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Development on the fiber-reinforced materials for low-voltage circuit breakers(I) (저압 배선용 차단기용 섬유강화 복합재료 개발(I))

  • Lee, Chang-R.;Song, Tae-H.;Kim, Jin-S.;Kim, Duck-J.;Lee, Doo-H.;Lee, Kwan-H.
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.127-129
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    • 2002
  • A new type of fiber-reinforced polymeric materials for the main body and the arc chamber of the low-voltage circuit breakers was developed. The tensile and the flectional strength of the three kinds of thermoplastic resins for the cover of MCCBs(Molded case circuit breakers) increase much higher than those made of BMC that has been used. In a high current-breaking test, an experimental MCCB with the new insulating material showed no-cracks on the bodies.

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Limiting method of short-circuit making current by controlling the time constant of dc component (단락시험 회로의 시정수 조정에 의한 투입전류 제한법)

  • Park, Seung-Jae;Ryou, Hyeong-Kee;Kang, Young-Sik;Koh, Heui-Seog
    • Proceedings of the KIEE Conference
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    • 2002.07a
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    • pp.466-468
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    • 2002
  • In order to newly define and specify the performance and the testing method of the high-voltage circuit breaker, IEC 62271-100 was published in May, 2001 and took place of IEC 60056 which had been used since 1987. This new standard intensifies the requirement and the test method of the circuit breaker and also domestic manufacturer makes progress the new product development. And, KERI also goes on the build-up project of short-circuit testing facilities for fulfilling the testing method requirements in new IEC 62271-100. This paper introduce the limiting method of short-circuit making current by controlling the time constant of dc component.

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