• Title/Summary/Keyword: implementation algorithm

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Design and Implementation of Public key-based Video Conference System for Authentication and Encryption (공개키기반 사용자인증과 암호화를 적용한 영상회의 시스템 설계 및 구현)

  • Jung Yong-Deug;Lee Sang-Hun;Jin Moon-Seog
    • The KIPS Transactions:PartC
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    • v.11C no.7 s.96
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    • pp.971-980
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    • 2004
  • This paper describes the design and implementation of the video conferencing system using public key infrastructure which is used for user authentication and encryption. Public key infrastructure reinforces the authentication process for conference participant, and the symmetric key system blocks malicious access to information and protect conference control information. This paper shows the implementation of the trans portation layer secure protocol in conformity with Korea public key authentication algorithm standard and symmetric encryption algorithm (DES, 3DES and AES) for media stream encryption. In this paper, we deal with two ways of protecting information : transportation layer secure protocol secures user authentication process and the conference control information; while public key-based authentication system protects personal information of users when they connect to the network. When distributing the session keys for encryption, Internet Key Exchange is used for P2P communication, and secure protocol is employed for 1 : N multi-user communication in the way of distributing the public key-based en-cryption key.

Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture (프로세서 구조에 따른 DCT 알고리즘의 구현 성능 비교)

  • Lee Jae-Seong;Pack Young-Cheol;Youn Dae-Hee
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6C
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    • pp.637-644
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    • 2006
  • This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.

On Efficient Algorithms for Generating Fundamental Units and their H/W Implementations over Number Fields (효율적인 수체의 기본단수계 생성 알고리즘과 H/W 구현에 관한 연구)

  • Kim, Yong-Tae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.6
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    • pp.1181-1188
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    • 2017
  • The unit and fundamental units of number fields are important to number field sieves testing primality of more than 400 digits integers and number field seive factoring the number in RSA cryptosystem, and multiplication of ideals and counting class number of the number field in imaginary quadratic cryptosystem. To minimize the time and space in H/W implementation of cryptosystems using fundamental units, in this paper, we introduce the Dirichlet's unit Theorem and propose our process of generating the fundamental units of the number field. And then we present the algorithm generating our fundamental units of the number field to minimize the time and space in H/W implementation and implementation results using the algorithm over the number field.

High Level Design and Performance Evaluation for the Implementation of WCDMA Base Station Modem (WCDMA 기지국 모뎀의 구현을 위한 상위 레벨 설계 및 통합 성능 평가)

  • Do Joo-Hyun;Lee Young-Yong;Chung Sung-Hyun;Choi Hyung-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1A
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    • pp.10-27
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    • 2005
  • In this paper, we propose a high level design architecture of WCDMA(UMTS) base station modem and synchronization algorithms applied to the proposed architecture. Also analysis of each synchronization algorithm and performance evaluation of fixed point designed modem are shown. Since the target system is base station modem, each synchronization algorithm is designed for its stable operation. To minimize implementation complexity, optimum fixed point design for best operation of synchronization algorithms is performed. We performed symbol level link simulation with fixed point designed modem simulator for data rate of 12.2kbps, 64kbps, 144kbps, and 384kbps. We compared performance results to the minimum requirements specified in 3GPP TS 25.104(Release 5). Extensive computer simulation shows that the proposed modem architecture has stable operation and outperform the minimum requirement by 2 dB. The proposed modem architecture has been applied in the implementation of WCDMA reverse link receiver modem chip successfully.

Implementation of a FLEX Protocol Signal Processor for High Speed Paging System (고속 페이징 시스템을 위한 FLEX 프로토콜 신호처리기의 구현)

  • Gang, Min-Seop;Lee, Tae-Eung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.69-78
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    • 2001
  • This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

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An Effective Parallel Implementation of Sound Synthesis of Guitar using GPU (GPU를 이용한 기타의 음 합성을 위한 효과적인 병렬 구현)

  • Kang, Sung-Mo;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.8
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    • pp.1-8
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    • 2013
  • This paper proposes an effective parallel implementation of a physical modeling synthesis of guitar on the GPU environment. We used appropriate filter coefficients and adjusted the length of delay line for each open string to generate 44,100 six-polyphonic guitar sounds (E2, A2, D3, G4, B3, E4) by using physical modeling synthesis. In addition, we analyzed the physical modeling synthesis algorithm and observed that we can exploit parallelism inherent in the length of delay line. Thus, we assigned CUDA cores as many as the length of delay line and effectively implemented the physical modeling synthesis using GPU to achieve the highest performance. Experimental results indicated that synthetic guitar sounds using GPU were very similar to the original sounds when we compared their spectra. In addition, GPU achieved 68x and 3x better performance than high-performance TI DSP and CPU, respectively. Furthermore, this paper implemented and evaluated the performance of multi-GPU systems for the physical modeling algorithm.

Design and Implementation of the Cdma2000 EV-DO security layer supporting Hardware using FPGA (FPGA를 이용한 Cdma2000 EV-DO 시큐리티 지원 하드웨어 설계 및 구현)

  • Kwon, Hwan-Woo;Lee, Ki-Man;Yang, Jong-Won;Seo, Chang-Ho;Ha, Kyung-Ju
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.18 no.2
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    • pp.65-73
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    • 2008
  • Security layer of the Cdma2000 1x EV-DO is currently completing standard (C.S0024-A v2.0). Accordingly, a hardware security devices, that allows to implementation requirement of the security layer described in standard document, is required to apply security function about data transferred between AT and AN of then Cdma2000 1x EV-DO environment. This paper represents design of hardware device providing EV-DO security with simulation of the security layer protocol via the FPGA platform. The SHA-1 hash algorithm for certification and service of packet data, and the AES, SEED, ARIA algorithms for data encryption are equip in this device. And paper represents implementation of hardware that applies optionally certification and encryption function after executing key-switch using key-switching algorithm.

A White Box Implementation of Lightweight Block Cipher PIPO (경량 블록 암호 PIPO의 화이트박스 구현 기법)

  • Ham, Eunji;Lee, Youngdo;Yoon, Kisoon
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.32 no.5
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    • pp.751-763
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    • 2022
  • With the recent increase in spending growth in the IoT sector worldwide, the importance of lightweight block ciphers to encrypt them is also increasing. The lightweight block cipher PIPO algorithm proposed in ICISC 2020 is an SPN-structured cipher using an unbalanced bridge structure. The white box attack model refers to a state in which an attacker may know the intermediate value of the encryption operation. As a technique to cope with this, Chow et al. proposed a white box implementation technique and applied it to DES and AES in 2002. In this paper, we propose a white box PIPO applying a white box implementation to a lightweight block cipher PIPO algorithm. In the white box PIPO, the size of the table decreased by about 5.8 times and the calculation time decreased by about 17 times compared to the white box AES proposed by Chow and others. In addition, white box PIPO was used for mobile security products, and experimental results for each test case according to the scope of application are presented.

Algorithm for Identifying Highway Horizontal Alignment using GPS/INS Sensor Data (GPS/INS 센서 자료를 이용한 도로 평면선형인식 알고리즘 개발)

  • Jeong, Eun-Bi;Joo, Shin-Hye;Oh, Cheol;Yun, Duk-Geun;Park, Jae-Hong
    • International Journal of Highway Engineering
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    • v.13 no.2
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    • pp.175-185
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    • 2011
  • Geometric information is a key element for evaluating traffic safety and road maintenance. This study developed an algorithm to identify horizontal alignment using global positioning system(GPS) and inertial navigation system(INS) data. Roll and heading information extracted from GPS/INS were utilized to classify horizontal alignment into tangent, circular curve, and transition curve. The proposed algorithm consists of two components including smoothing for eliminating outlier and a heuristic classification algorithm. A genetic algorithm(GA) was adopted to calibrate parameters associated with the algorithm. Both freeway and rural highway data were used to evaluate the performance of the proposed algorithm. Promising results, which 90.48% and 88.24% of classification accuracy were obtainable for freeway and rural highway respectively, demonstrated the technical feasibility of the algorithm for the implementation.

A Study on Developing an Efficient Algorithm for the p-median Problem on a Tree Network (트리 네트워크 상에서의 p-미디안 문제에 대한 효율적인 알고리즘 개발에 관한 연구)

  • Cho, Geon
    • Journal of the Korean Operations Research and Management Science Society
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    • v.29 no.1
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    • pp.57-70
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    • 2004
  • Given a tree network on which each node has its own demand and also stands for a candidate location of a potential facility. such as plant or warehouse, the f-median problem on the network (PMPOT) is to select less than or equal to P number of facility locations so that the whole demand on a node is satisfied from only one facility and the total demand occurred on the network can be satisfied from those facilities with the minimum total cost, where the total cost Is the sum of transportation costs and the fixed costs of establishing facilities. Tamir(1996) developed an O(p n$^2$) algorithm for PMPOT which is known to be the best algorithm In terms of the time complexity, where n is the number of nodes in the network, but he didn't make any comments or explanation about implementation details for finding the optimal solution. In contrast to Tamir's work, Kariv and Hakimi(1979) developed O(p$^2$n$^2$) algorithm for PMPOT and presented O(n$^2$) algorithm for finding the optimal solution in detail. In this paper, we not only develop another O(p n$^2$) dynamic programming algorithm for PMPOT that is competitive to Tamir's algorithm in terms of the time complexity, but also present O(n) algorithm that is more efficient than kariv and Hakimi's algorithm in finding the optimal solution. finally, we implement our algorithm on a set of randomly generated problems and report the computational results.