• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1157-1162
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• 2015

This paper is the design and implementation to the 4x4 MIMO algorithm based on OFDM, and presented how to verify the implemented result. Algorithm applied the MRVD and QRM-MLD. Matlab and Simulink are used to design channel presumption & MIMO algorithm by Floating-point and Fixed-point model. After then implement VHDL using Modelsim. Performance of algorithm is checked by comparing Simulink model, Modelsim simulation, ISE ChipScope with the result measured by oscilloscope. This method is useful to verify an algorithm with uncompleted system. Conformance between the result of ChipScope and the result of oscilloscope is confirmed, it could be applied on the Backhaul system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1785-1794
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• 1999

The affine projection algorithm has known t require less computational complexity than RLS but have much faster convergence than NLMS for speech-like input signals. But the affine projection algorithm is still much more computationally demanding than the LMS algorithm because it requires the matrix inversion. In this paper, we show that the affine projection algorithm can be realized with the Gram-Schmidt orthogonalizaion of input vectors. Using the derived relation, we propose an approximate but much more efficient implementation of the affine projection algorithm. Simulation results show that the proposed algorithm has the convergence speed that is comparable to the affine projection algorithm with only a slight extra calculation complexity beyond that of NLMS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1533-1545
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• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1620-1632
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• 1998

This paper presents a fast parallel algorithm for volume rendering and its implementation using C language and MPI MasPar Programming Language) on the 4,096 processor MasPar MP-2 machine. This parallel algorithm is a parallelization hased on the Lacroute' s sequential shear - warp algorithm currently acknowledged to be the fastest sequential volume rendering algorithm. This algorithm reduces communication overheads by using the sheared space partition scheme and the load balancing technique using load estimates from the previous iteration, and the number of voxels to be processed by using the run-length encoded volume data structure.Actual performance is 3 to 4 frames/second on the human hrain scan dataset of $128\times128\times128$ voxels. Because of the scalability of this algorithm, performance of ]2-16 frames/sc.'cond is expected on the 16,384 processor MasPar MP-2 machine. It is expected that implementation on more current SIMD or MIMD architectures would provide 3O~60 frames/second on large volumes.

• MALSORI
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• no.50
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• pp.123-137
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• 2004

In this paper, we consider the implementation of connected digit recognition system using tree structured lexicon model. To implement efficiently the fixed or variable length digit recognition system, finite state network (FSN) is required. We merge the word network algorithm that implements the FSN with lexical tree search algorithm that is used for general speech recognition system for fast search and large vocabulary systems. To find the efficient modeling of digit recognition system, we investigate some performance changes when the lexical tree search is applied.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.1-6
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• 1998

To achieve fast control action, direct control methods should be used. "Direct Mean Torque Control" (DMTC) combines the good dynamic performance of Direct Torque Control (DTC) with the advantages of inherently constant switching frequency and time equidistant control for implementation in a digital signal processor. Since DMTC is a predictive control algorithm, the model and its correction deserves special investigations. This paper proposes a steady-state Kalman filter which is well suited for fast computation.mputation.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.129-132
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• 1991

In this paper, the active noise controll system in duct is analyzed with real time implementation. The primary noise signal detected by microphone is modeled using adaptive algorithm and the secondary signal which has the same amplitude and 180$^{\circ}$phase shift with the primary noise signal is generated in the controller. We used the DSP56001 as a real-time processor and LMS algorithm as a adaptive technique, the experimental results shows that our system can reduce the noise level in duce to 15~40[db].

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.463-464
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• 2007

This paper presents the hardware-based genetic algorithm, written in VHDL. Due to parallel computation and no function call overhead, a hardware-based GA advantage a speedup over a software-based GA. The proposed architecture is constructed on a field-programmable gate arrays, which are easily reconfigured. Since a general-purpose GA requires that the fitness function be easily changed, the hardware implementation must exploit the reprogrammability.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.565-570
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• 1986

In this paper, the implementation of a voiced/unvoiced/silence discrimination system is presented. The algorithm is based on the zerocrossing rate and the spectral energy distribution of speech. In measuring zerocrossing rate, a new frequency-to-voltage conversion type interval filter is used. Expermental results show that with the proposed algorithm the effect of impulse noise in voiced intervals can be removed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1928-1934
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• 1993

This paper presents a fast algorithm of integer discrete cosine transform(IDCT) allowing VLSI implementation by integer arithmetic. The proposed fast algorithm has been developed using Chen`s matrix decomposition in DCT, and requires less number of arithmetic operations compared to the IDCT. In the presented algorithm, the number of addition number is the same as the one of Chen`s algorithm if DCT, and the number of multiplication if the same as that in DCT at N=8 but drastically decreasing when N is above 8. In addition, the drawbacks of DCT such as performance degradation at the finite length arithmetic could be overcome by the IDCT.