• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.343-356
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• 1991

An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. The development time and cost for implementing a high speed signal processing system can be considerably reduced because algorithm are implemented in software using commercially available digital signal processors. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach not only requires a simple interconnection network but also reduces the number of communications among the processors very much. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors in the system. A systematic scheduling method has been developed by using a processors which can be used efficiently, the methods for solving dependency problems between the processors are investigated. Implementation procedures and results for FIR, recursive (IIR), and adaptive filtering algorithms are illustrated.

• Journal of the Korea Society for Simulation
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• v.8 no.2
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• pp.57-72
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• 1999

With the rapidly increasing complexity of decision-marking or system development in the fields of industry, management, etc., modelling techniques using simulation has become more highlighted. Particularly, the advent of parallel computer systems not only has opened a new horizon of parallel simulation, but also has greatly contributed to the speed-up of the execution of simulation. The implementation of parallel simulation, however, is not a easy job for those who accustomed to the existing computer systems. And it is also necessarily confronted with the problem of synchronization conflict in the process. Thus, how to allow a wider community of users to gain access to parallel simulation while solving synchronization conflicts has become an important issue in simulation study. As a method to solve these problems, this paper is primarily concerned with the implementation of GPSS which is a generally used simulation language for discrete event simulation, onto a parallel computer using C-LINDA. For that, this paper, is to suggest a model and algorithm and to experiment it using a case.

• ETRI Journal
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• v.41 no.6
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• International Journal of Control, Automation, and Systems
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• v.4 no.5
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• ETRI Journal
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• v.37 no.4
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• pp.667-676
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• 2015

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.1
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• pp.37-45
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• 2016

In this paper, design and implementation issues for a network-oriented RF emitter localization system with array antenna are discussed. For hardware, the problem of array mismatch and RF/IF channel mismatch are introduced and the calibration schemes for solving those problems are also provided. For software, it is explained how to overcome the drawback of conventional MUltiple Signal Identification and Classification (MUSIC) algorithm in a point of identifying the number of received signals and problems such as Data Association Problem and Ghost Node Problem in regard to multiple emitter localization are presented with some approaches for getting around those problems. Finally, for implementation, a criterion for arranging each of sensors and a requirement for alignment of array antenna' orientation are also given.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.12
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• pp.1034-1039
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• 2016

This paper presents the implementation and control of a small-scaled excavator system. The commercial miniature of an excavator system has been modified and its control hardware is embedded to access the feedback control. Encoder sensors are attached to the joint and a force sensor is mounted on the end-effector so that feedback position control is accessible as well as force control. The dynamic model of the excavator system is derived as a four linkage robot arm and its control performances are simulated. Experimental studies of contact force control tasks are conducted to test the control algorithm for the excavator system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.8
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• pp.492-499
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• 2003

This paper presents the analysis and the implementation of the asynchronous communication portion of the IEEE 802.11 MAC protocol. We have used PRISM2 chipsets from INTERSIL to build baseband, IF, and RF parts and PCI controller from PLX to interface LLC Layer. We have implemented DCF(Distributed Coordination Function) service using CSMA/CA(Carrier Sense Multiple Access with Collision Acoidance) with backoff algorithm and RTS/CTS protocol. Also, we have implemented TSF(Timing Synchronization Function) which can be used for power management frequency hop synchronization, and other management function. This study can be used as a reference for the MAC protocol implementation and MAC controller design in very high speed wireless LAN which complies with the IEEE 802.11 standard.

• Journal of information and communication convergence engineering
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• v.2 no.3
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• pp.177-181
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• 2004

In this paper, we suggest an Iris recognition system with an excellent recognition rate and confidence as an alternative biometric recognition technique that solves the limit in an existing individual discrimination. For its implementation, we extracted coefficients feature values with the wavelet transformation mainly used in the signal processing, and we used neural network to see a recognition rate. However, Scale Conjugate Gradient of nonlinear optimum method mainly used in neural network is not suitable to solve the optimum problem for its slow velocity of convergence. So we intended to enhance the recognition rate by using Levenberg-Marquardt Back-propagation which supplements existing Scale Conjugate Gradient for an implementation of the iris recognition system. We improved convergence velocity, efficiency, and stability by changing properly the size according to both convergence rate of solution and variation rate of variable vector with the implementation of an applied algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.387-393
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• 1987

The introduction of a digiral subscriber loop transmission system necessitates an optimized line interface solution. To meet this objective an adaptive line equalizer has been developed. The equalizer can be compensated up to 42 dB line loss at 200KHz, and operated up to 3.2 Km transmission length (0.4 mm\ulcornercable)at a rate of 400Kb/s. This has been builted using a variable \ulcorner equalizer to compensate a frequency-attenuation characteristics of metallic cable, an AGC (automatic gain control) circuits with simple control algorithm, and various filters to minimize a transmission constraints over subscriber loop. The purpose of this paper is to present a short description of a design of the adaptive line equalizer with a summary of implementation results. Some design concepts and considerations which results in an implementation of the equalizer are also given.