• Title/Summary/Keyword: implementation algorithm

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Development of a Controller for an Educational Robot and Implementation of a Fuzzy Algorithm (교육용 로보트의 제어기 개발 및 퍼지 알고리즘의 구현)

  • Lee, Jun-Bae;Kim, Sung-Hyun;Kim, Do-Hyun;Ahn, Hyun-Sik
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1219-1221
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    • 1996
  • In this paper, we develop a control system of an Educational Robot and implement a fuzzy algorithm for the position control. The MA2000 robot manufactured by TecQuipment Co. is the controlled system and 3 axes(waist, shoulder, elbow) of total 6 axes are controlled by the fuzzy logic-based algorithm. The control system consists of an IBM PC, an interface board capable of A/D conversion and PWM generation, and a drive board for dc motors in joints of the robot. The experiments show that the modified fuzzy algorithm yields a better performance in steady-stale than that of the conventional fuzzy algorithm.

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A Study on Implementation of a Real Time Learning Controller for Direct Drive Manipulator (직접 구동형 매니퓰레이터를 위한 학습 제어기의 실시간 구현에 관한 연구)

  • Jeon, Jong-Wook;An, Hyun-Sik;Lim, Mee-Seub;Kim, Kwon-Ho;Kim, Kwang-Bae;Lee, Kwae-Hi
    • Proceedings of the KIEE Conference
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    • 1993.07a
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    • pp.369-372
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    • 1993
  • In this thesis, we consider an iterative learning controller to control the continuous trajectory of 2 links direct drive robot manipulator and process computer simulation and real-time experiment. To improve control performance, we adapt an iterative learning control algorithm, drive a sufficient condition for convergence from which is drived extended conventional control algorithm and get better performance by extended learning control algorithm than that by conventional algorithm from simulation results. Also, experimental results show that better performance is taken by extended learning algorithm.

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Interface Specification Modeling for Distributed Network Management Agent of IMT-2000 Based on Applicable Service Independent Building Blocks (Applicable SIB에 의한 IMT-2000 분산 망관리 에이전트의 인터페이스 스펙 모델링)

  • Park, Soo-Hyun
    • Journal of Information Technology Services
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    • v.1 no.1
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    • pp.119-139
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    • 2002
  • It is noteworthy that IMT -2000 communication network based on All-HP/AIN(Advanced Intelligent Network) should accomodate current and future wire/wireless AIN service easily through integration and gearing AIN construction elements. In this paper. Intelligent Farmer model(I-Farmer Model) and methodology are suggested in order to solve the several problems including standardization on implementation of Q3 interface in Telecommunication Management Network(TMN) agents which is caused by heterogeneous platform environment and future maintenance. Also this paper proposes ITI algorithm transforming the system which is designed by I-Farmer model to Interface Specification Model(ISM) applying the I-Farmer model. In addition to ITI algorithm. we suggest NTS(Node to SIB) algorithm converting entity node and ILB/OLB component in agent system designed by the I-Farmer model to SIB of AIN GFP(Global Functional Plane) and to ASIB for application program.

Implementation of GA Processor for Efficient Sequence Generation (효율적인 DNA 서열 생성을 위한 진화연산 프로세서 구현)

  • Jeon, Sung-Mo;Kim, Tae-Seon;Lee, Chong-Ho
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.376-379
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    • 2003
  • DNA computing based DNA sequence Is operated through the biology experiment. Biology experiment used as operator causes illegal reactions through shifted hybridization, mismatched hybridization, undesired hybridization of the DNA sequence. So, it is essential to design DNA sequence to minimize the potential errors. This paper proposes method of the DNA sequence generation based evolutionary operation processor. Genetic algorithm was used for evolutionary operation and extra hardware, namely genetic algorithm processor was implemented for solving repeated evolutionary process that causes much computation time. To show efficiency of the Proposed processor, excellent result is confirmed by comparing between fitness of the DNA sequence formed randomly and DNA sequence formed by genetic algorithm processor. Proposed genetic algorithm processor can reduce the time and expense for preparing DNA sequence that is essential in DNA computing. Also it can apply design of the oligomer for development of the DNA chip or oligo chip.

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Structural damage detection based on Chaotic Artificial Bee Colony algorithm

  • Xu, H.J.;Ding, Z.H.;Lu, Z.R.;Liu, J.K.
    • Structural Engineering and Mechanics
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    • v.55 no.6
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    • pp.1223-1239
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    • 2015
  • A method for structural damage identification based on Chaotic Artificial Bee Colony (CABC) algorithm is presented. ABC is a heuristic algorithm with simple structure, ease of implementation, good robustness but with slow convergence rate. To overcome the shortcoming, the tournament selection mechanism is chosen instead of the roulette mechanism and chaotic search mechanism is also introduced. Residuals of natural frequencies and modal assurance criteria (MAC) are used to establish the objective function, ABC and CABC are utilized to solve the optimization problem. Two numerical examples are studied to investigate the efficiency and correctness of the proposed method. The simulation results show that the CABC algorithm can identify the local damage better compared with ABC and other evolutionary algorithms, even with noise corruption.

Enhanced technique for Arabic handwriting recognition using deep belief network and a morphological algorithm for solving ligature segmentation

  • Essa, Nada;El-Daydamony, Eman;Mohamed, Ahmed Atwan
    • ETRI Journal
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    • v.40 no.6
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    • pp.774-787
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    • 2018
  • Arabic handwriting segmentation and recognition is an area of research that has not yet been fully understood. Dealing with Arabic ligature segmentation, where the Arabic characters are connected and unconstrained naturally, is one of the fundamental problems when dealing with the Arabic script. Arabic character-recognition techniques consider ligatures as new classes in addition to the classes of the Arabic characters. This paper introduces an enhanced technique for Arabic handwriting recognition using the deep belief network (DBN) and a new morphological algorithm for ligature segmentation. There are two main stages for the implementation of this technique. The first stage involves an enhanced technique of the Sari segmentation algorithm, where a new ligature segmentation algorithm is developed. The second stage involves the Arabic character recognition using DBNs and support vector machines (SVMs). The two stages are tested on the IFN/ENIT and HACDB databases, and the results obtained proved the effectiveness of the proposed algorithm compared with other existing systems.

Improvement of Wi-Fi Location Accuracy Using Measurement Node-Filtering Algorithm

  • Do, Van An;Hong, Ic-Pyo
    • Journal of IKEEE
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    • v.26 no.1
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    • pp.67-76
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    • 2022
  • In this paper, we propose a new algorithm to improve the accuracy of the Wi-Fi access point (AP) positioning technique. The proposed algorithm based on evaluating the trustworthiness of the signal strength quality of each measurement node is superior to other existing AP positioning algorithms, such as the centroid, weighted centroid, multilateration, and radio distance ratio methods, owing to advantages such as reduction of distance errors during positioning, reduction of complexity, and ease of implementation. To validate the performance of the proposed algorithm, we conducted experiments in a complex indoor environment with multiple walls and obstacles, multiple office rooms, corridors, and lobby, and measured the corresponding AP signal strength value at several specific points based on their coordinates. Using the proposed algorithm, we can obtain more accurate positioning results of the APs for use in research or industrial applications, such as finding rogue APs, creating radio maps, or estimating the radio frequency propagation properties in an area.

Imaging Method for Array Structured Bistatic Ground-to-Air Radar (배열 구조 바이스태틱 지대공 레이다의 이미징 기법)

  • Choi, Sang-Hyun;Yang, Dong-Hyeuk;Song, Ji-Min;Yang, Hoon-Gee
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.8
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    • pp.599-607
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    • 2018
  • This paper presents a ground-to-air bistatic radar system and its implementation algorithm, which resembles an SAR(synthetic aperture radar) reconstruction algorithm. Via cooperative working between a standoff transmitting radar and an array of ground based receiving radars, it detects and images moving targets under clutter in the air. In the proposed system, the whole receiving antenna aperture is synthesized by physical ground based radars, and thus, unlike conventional SAR, it does not require long illumination time of the target area. The reconstruction algorithm uses planewave approximation based polar format processing, which alleviates the requirement of positioning the receiving radars, which can cause grating lobes if not chosen properly. We derive a reconstruction algorithm including clutter suppression and discuss implementation issues, such as the resolution of a reconstructed image and the method of compensation for the irregularity of the receiving radars' positions. A simulation that validates the proposed algorithm is also shown.

Design and FPGA Implementation of a High-Speed RSA Algorithm for Digital Signature (디지털 서명을 위한 고속 RSA 암호 시스템의 설계 및 FPGA 구현)

  • 강민섭;김동욱
    • The KIPS Transactions:PartC
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    • v.8C no.1
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    • pp.32-40
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    • 2001
  • In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

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An efficient hardware implementation of 64-bit block cipher algorithm HIGHT (64비트 블록암호 알고리듬 HIGHT의 효율적인 하드웨어 구현)

  • Park, Hae-Won;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.1993-1999
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    • 2011
  • This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.