• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 1992.11a
• /
• pp.127-130
• /
• 1992

GF(2m) 이론은 switching 이론과 컴퓨터 연산, 오류 정정 부호(error correcting codes), 암호학(cryptography) 등에 대한 폭넓은 응용 때문에 주목을 받아 왔다. 특히 유한체에서의 이산 대수(discrete logarithm)는 one-way 함수의 대표적인 예로서 Massey-Omura Scheme을 비롯한 여러 암호에서 사용하고 있다. 이러한 암호 system에서는 암호화 시간을 동일하게 두면 고속 연산은 유한체의 크기를 크게 할 수 있어 비도(crypto-degree)를 향상시킨다. 따라서 고속 연산의 필요성이 요구된다. 1981년 Massey와 Omura가 정규기저(normal basis)를 이용한 고속 연산 방법을 제시한 이래 Wang, Troung 둥 여러 사람이 이 방법의 구현(implementation) 및 곱셈기(Multiplier)의 설계에 힘써왔다. 1988년 Itoh와 Tsujii는 국제 정보 학회에서 유한체의 역원을 구하는 획기적인 방법을 제시했다. 1987년에 H, W. Lenstra와 Schoof는 유한체의 임의의 확대체는 원시정규기저(primitive normal basis)를 갖는다는 것을 증명하였다. 1991년 Stepanov와 Shparlinskiy는 유한체에서의 원시원소(primitive element), 정규기저를 찾는 고속 연산 알고리즘을 개발하였다. 이 논문에서는 원시 정규기저를 찾는 Algorithm을 구현(Implementation)하고 이것이 응용되는 문제들에 관해서 연구했다.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.3
• /
• pp.16-23
• /
• 1998

In this paper, we present a fast and efficient Iterative Improvement Partitioning(IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. The IIP algorithms are very widely used in VLSI circuit partition due to their time efficiency. As the performance of these algorithms depends on choices of moving cell, various methods have been proposed. Specially, Cluster-Removal algorithm by S. Dutt significantly improved partition quality. We indicate the weakness of previous algorithms wjere they used a uniform method for choice of cells during for choice of cells during the improvement. To solve the problem, we propose a new IIP technique that selects the method for choice of cells according to the improvement status and present hybrid bucket structures for easy implementation. The time complexity of proposed algorithm is the same with FM method and the experimental results on ACM/SIGDA benchmark circuits show improvment up to 33-44%, 45%-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with less CUP tiem, it outperforms Paraboli and MELO represented constructive-partition methods by about 12% and 24%, respectively.

• Proceedings of the KIEE Conference
• /
• 2001.07d
• /
• pp.2738-2740
• /
• 2001

This paper describes a study on implementation of image processing systems for the defect inspection of polyethylene. In order to detect the edge, the Robert filter is used. And we use to the labeling algorithm for feature extraction. Labeling the conected regions of a image is a fundamental computation in image analysis and machine vision, with a large number of application. This algorithm is designed for the defect inspection of polyethylene.

• Proceedings of the KIPE Conference
• /
• 2001.07a
• /
• pp.372-376
• /
• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.4
• /
• pp.961-971
• /
• 1996

The effect of inband TDMA narrow band jammers to DS-CDMA system performance and the suppression techniques are investigated using Monte Carlo simulations. TIA stantard North American Digital Cellular wea used as jammer. Levinson Dubin and conventional recursive least square algorithm were emphasized since these techniques can be implemented with a few DSPs for CDMA application. Two filter structures, i.e., complex suppression filter and real suppression filter in each inphase and quadrature channels, are investigated and their performances are compared. Complex suppression filter with Levinson Durbin algorithm of 20msec updata rate is the most promising with respect to implementation and performance poit of view. Implementation feasibility is discussed and the channel capacity lost by suppression is computed.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.40 no.4
• /
• pp.331-341
• /
• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• Proceedings of the KOSOMBE Conference
• /
• v.1993 no.11
• /
• pp.151-155
• /
• 1993

Evoked potentials(EP) measured with scalp electrodes are often described as a deterministic process corrupted by uncorrelated electrical activities occuring in the brain and These electrical activities(ongoing EEG) refer to noise in EP recording. The Conventional method to determine the EP waveform requires long recording time. Unfortunately most of algorithm developed are too complicated for implementation in real time. Thus, conner EP recording devices use Ensemble average for real time processing. In this paper introduce EP recording hardware for processing advanced algorithm in real tlne. This hardware is composed of DSP chip(TMS320c25) and microcomputer.

• Journal of Information Processing Systems
• /
• v.13 no.1
• /
• pp.104-113
• /
• 2017

In this paper, we present an approach to transmit data from the source to the destination through a minimal path (least-cost path) in a computer network of n nodes. The motivation behind our approach is to address the problem of finding a minimal path between the source and destination. From the work we have studied, we found that a Steiner tree with bounded Steiner vertices offers a good solution. A novel algorithm to construct a Steiner tree with vertices and bounded Steiner vertices is proposed in this paper. The algorithm finds a path from each source to each destination at a minimum cost and minimum number of Steiner vertices. We propose both the sequential and parallel versions. We also conducted a comparative study of sequential and parallel versions based on time complexity, which proved that parallel implementation is more efficient than sequential.

• The Journal of Information Technology
• /
• v.9 no.1
• /
• pp.33-39
• /
• 2006

This study is for the contents of development to the hardware system and software driving algorithm to implement the frequency band of about 7KHz los pass digital filter which has the cut-off frequency of 392Hz by interfacing of a microprocessor with its peripheral analog-to-digital converter chip and digital-to-analog converter chip. The simplicity of digital filter design without difficulty and the implementation of programmed digital filter can be realized by providing the interfacing method to implement the law pass digital filter for the biological signals and the realization method of computer algorithm by a microprocessor.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1086-1087
• /
• 2007

This paper presents a implementation of speed sensorless vector control algorithm of induction motor using MATLAB/SIMULINK. The proposed method utilize the combination of the voltage model based on stator equivalent model and the current model based on rotor equivalent model, which enables stable estimation of rotor flux. Estimated rotor speed, which is used to speed controller of induction motor, is based on estimated flux. The overall system consisted of speed controller with the most general PI controller, current controller, flux controller. Speed sensorless vector control algorithm is implemeted as block diagrams using MATLAB/SIMULINK. Realtime control is perform by dSPACE DS1104 control board and Real-Time-Interface(RTI).