• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.1
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• pp.41-51
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• 2018

Format preserving encryption(FPE) performs encryption with preserving the size and format of plain-text. Therefore, it is possible to minimize the structural change of the database before and after the encryption. For example, when encrypting data such as credit card number or social security number, it is possible to maintain the existing database structure because FPE outputs the same form of cipher-text as plain-text. Currently, the National Institute of Standards and Technology (NIST) recommends FF1 and FF3 as standards for FPE. Recently, in Korea, FEA, which is a very efficient FPE algorithm, has been adopted as the standard of FPE. In this paper, we analyze FEA and measure the performance of FEA by optimizing it in various environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.1983-1988
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• 2006

There are gradually built on electronic commerce and business information system for the effective and automated use of internet while the mainstream of industry moves on information. It is necessary that a company should develop a electronic approval system because the business documents have application to an electronic commerce, business information system as well Currently, electronic approval system on groupware is using the way of inserting the image of an approval signature, which is vulnerable on a security by attacks of fraudulent use of electrical signature and eavesdropping on electronic documents. In this paper, we implementation XML form generator based on DTD having business documents structure for creating a valid business XML documents. we designed electronic approval system based on secured XML which transfers encrypted documents. For the security issues of written XML business documents, it makes use of the crypto algorithm having high performance transaction by the interchange of public key between a server and a client.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.1
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• pp.13-19
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• 2011

In this paper, a visual surveillance system using SOPC based NIOS II embedded processor and C2H compiler was implemented. In this system, the IP is constructed by C2H compiler for the output of the camera images, image processing, serial communication and network communication, then, it is implemented to effectively control each IP based on the SOPC and the NIOS II embedded processor. And, an algorithm which updates the background images for high speed and robust detection of the moving objects is proposed using the Adaptive Gaussian Mixture Model(AGMM). In results, it can detecte the moving objects(pedestrians and vehicles) under day-time and night-time. It is confirmed that the proposed AGMM algorithm has better performance than the Adaptive Threshold Method(ATM) and the Gaussian Mixture Model(GMM) from our experiments.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.1433-1435
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• 2003

Very decisive progress was made in advancing fundamental POL-IN-SAR theory and algorithm development during the past decade. This was accomplished with the aid of airborne & shuttle platforms supporting single -to-multi-band multi-modal POL-SAR and also some POL-IN-SAR sensor systems, which will be compared and assessed with the aim of establishing the hitherto not completed but required missions such as tomographic and holographic imaging. Because the operation of airborne test-beds is extremely expensive, aircraft platforms are not suited for routine monitoring missions which is better accomplished with the use drones or UAVs. Such unmanned aerial vehicles were developed for defense applications, however lacking the sophistic ation of implementing advanced forefront POL-IN-SAR technology. This shortcoming will be thoroughly scrutinized resulting in the finding that we do now need to develop most rapidly POL-IN-SAR drone-platform technology especially for environmental stress-change monitoring with a great variance of applications beginning with flood, bush/forest-fire to tectonic-stress (earth-quake to volcanic eruptions) for real-short-time hazard mitigation. However, for routine global monitoring purposes of the terrestrial covers neither airborne sensor implementation - aircraft and/or drones - are sufficient; and there -fore multi-modal and multi-band space-borne POL-IN-SAR space-shuttle and satellite sensor technology needs to be further advanced at a much more rapid phase. The existing ENVISAT with the forthcoming ALOSPALSAR, RADARSAT-2, and the TERRASAT will be compared, demonstrating that at this phase of development the fully polarimetric and polarimetric-interferometric modes of operation must be viewed and treated as preliminary algorithm verification support modes and at this phase of development are still not to be viewed as routine modes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10A
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• pp.780-787
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• 2003

Adaptive modulation is the method to increase the throughput of the mobile system using the power margin of the system design. In this paper, we propose the method to change adaptive modulation parameters for the stable system operation by monitoring the mobility of the mobile station. The proposed method measures the instanteneous mobility of the mobile station monitoring the closed power control data. The MPSK modulation method is used for the basic modulation method because of the hardware implementation. Using the proposed method we can get the more powerful throughput. By the system simulation to verify the evaluation of the proposed algorithm, we can notice the algorithm is more efficient than the typical method

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.2
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• pp.18-28
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• 2006

We consider a Direct Input Output Manufacturing System(DIOMS) which has a munber of machine centers placed along a built-in Automated Storage/Retrieval System(AS/RS). The Storage/Retrieval (S/R) machine handles parts placed on pallets for the operational aspect of DIOMS and determines the optimal operating policy by combining computer simulation and genetic algorithm. The operational problem includes: input sequencing control, dispatching rule of the S/R machine, machine center-based part type selection rule, and storage assignment policy. For each operating policy, several different policies are considered based on the known research results. In this paper, using the computer simulation and genetic algorithm we suggest a method which gives the optimal configuration of operating policies within reasonable computation time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.611-619
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• 2008

2.5D Mapping system that embody in this paper can make new design by doing draping to live various texture and model picture image of fashion clothes by pattern, and can confirm clothes work to simulation without producing direction sample or product directly. Also, the system can support function that can forecast fabric design and state of end article exactly, and the system can bring competitive power elevation of fashion industry and cost-cutting effect by doing draping using database of fabric and model picture image. 2.5D Mapping system composed and embodied by mesh warp algorithm module, light and shade extraction and application module, mapping path extraction module, mesh creation and transformation module, and 2.5D mapping module for more natural draping. Future work plans to study 3D fashion design system that graft together 3D clothes technology and 3D human body embodiment technology to do based on embodiment technology of 2.5D mapping system and overcomes expression limit of 2.5D mapping technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.