• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.79-88
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• 2007

Demand for the technology for access to device control network in industry and for access to building automation system via internet is on the increase. In such technology integration of a device control network with a data network such as internet and organizing wide-ranging DCS(distributed control system) is needed, and it can be realized in the framework of VDN(virtual device network)[1,2]. Specifications for device control network and data network are quite different because of the differences in application. So a router that translates the communication protocol between device control network and data network and efficiently transmits information to destination is needed for implementation of the VDN, This paper proposes the concept of NCS(networked control system) based on VDN(virtual device network) and suggests the routing algorithm that uses embedded system.[3]

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.451-465
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• 1987

With the introduction of ISDN network, the D channel protocol has bee defined as a signalling method for ISDN user-network interface. Therefore the NT2(Network Termination 2) which carry out concentration and switching function, must process the D channel related information. This paper describes how the D channel protocoal is applied and implented in a small ISDN subscriber concentrating system that has NT2 functions. The application protocol proposed is addressed taking into consideration the compatibility with ISDN standard facilities, TE(Terminal Equipment) or ET(Exchange Terminator), This protocol has been implementes using a general multitask operating system and it has the features of the minimized information processing and the simpified algorithm which are suitable for a small system. Its application programs are divided into various tasks to facilitate the addition and the modification of function. In this paper, we briefly outline the protocol defined in CCITT and show the application protocol that has fitted in a small concentrating system with NT2 functions. Also we present the experimental results and implementation method of this protocol.

• Geophysics and Geophysical Exploration
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• v.10 no.2
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• pp.124-130
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• 2007

Least squares ($l^2$ norm) solutions of seismic inversion tend to be very sensitive to data points with large errors. The $l^1$ norm minimization gives more robust solutions, but usually with higher computational cost. Iteratively reweighted least squares (IRLS) method gives efficient approximate solutions of these $l^1$ norm problems. I propose an efficient implementation of the IRLS method for a hybrid $l^1/l^2$ minimization problem that behaves as $l^2$ norm fit for small residual and $l^1$ norm fit for large residuals. The proposed algorithm shows more robust characteristics to the decision of the threshold value than the l1 norm IRLS inversion does with respect to the threshold value to avoid singularity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.81-89
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• 2007

The Viterbi decoder, which employs the maximum likelihood decoding method, is a critical component in forward error correction for digital communication system. However, lowering power consumption on the Viterbi decoder is a difficult task since the number of paths calculated equals the number of distinctive states of the decoder and the Viterbi decoder utilizes trace-back method. In this paper, we propose a method which minimizes the number of operations performed on the comparator, deployed in the SPEC-T Viterbi decoder implementation. The proposed comparator was applied to the ACSU(Add-Compare-Select Unit) and MPMSU(Minimum Path Metric Search Unit) modules on the decoder. The proposed ACS scheme and MPMS scheme shows reduced power consumption by 10.7% and 11.5% each, compared to the conventional schemes. When compared to the SPEC-T schemes, the proposed ACS and MPMS schemes show 6% and 1.5% less power consumption. In both of the above experiments, the threshold value of 26 was applied.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.33-41
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• 2008

Telematics system includes the "vehicle remote diagnosis technology", "driving pattern analysis technology" which are commercially attractive in the real life. To implement those technologies, we need vehicle signal interface, vehicle diagnosis interface, accelerometer/yaw-rate sensor interface, GPS data processing, driving pattern analysis, and CDMA data processing technique. Based on these technologies, we analyze the error existence by diagnosing the EMS(Engine Management System), TMS(Transmission Management System), ABS/TCS, A/BAG in real time. And we are checking about a driving pattern and management of the vehicle, which are sent to the information center through the wireless communication. These database results will make the efficient vehicle and driver management possible. We show the effectiveness of our results by field driving test after completing the H/W & S/W design and implementation for vehicle remote diagnosis and driving pattern analysis.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.846-853
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• 2004

This paper introduces implementation of a traffic distributed processing system on the Web Sever Networking. The study used two software packages （Packet Capture and Round-Robin Test Package） to check packet quantity from Virtual Network Structure (data generator, virtual server, Serve. 1, 2, 3), and could find out traffic distribution toward Server 1, 2, and 3. The functions of implemented Round-Robin Load Balancing Monitoring System include Round-Robin testing, system monitoring, and graphical indication of data transmission/packet quantity (figures ＆ diagram). As the result of the study shows, Round-Robin Algorithm ensured definite traffic distribution, unless incoming data loads differ much. Although error levels were high in some cases, they were eventually alleviated by repeated tests for a long period of time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.116-120
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• 2011

In this paper, we have designed and implemented the integrated protocol gateway for the integration of CAN and Profibus networks. To do that, we used the Switched Ethernet as Backbone network, and each fieldbus network is connected by CAN/Ethernet or Profibus/Ethernet gateway, and each gateway perform the translation between fieldbus and Ethernet frames. Futhermore, we realized the real-time features in the environment of the Switched Ethernet by applying the distributed hard real-time scheduling algorithm among each gateways. To implement tht CAN/Ethernet and Profibus/Ethernet gateways, we used the Linux of kernel 2.6.31.12 real-time patched version(PREEMTED_RT), and we could verify successful message translation and real-time features through real implementation.