• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.21-30
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• 1990

This paper describes a hardware implementation of the interframe monochrome video CODEC using a MC-CVQ(Motion Compensated and Classified Vector Quantization) algorithm. The specifications of this CODEC are (1) the resolution of image is $128{\times}128$ pixels, and (2) the transmission rates are about 10frames/sec at the 64Kbps channel. In order to design the CODEC under these conditions, it is implemented by a multiprocessor system composed of MC unit, CVQ nuit and decoder unit, which are controlled by microprogramming technique. And the 3~stage pipelined ALU(Arithmetic and Logic Unit) is adopted to calculate the minimum error distance in the MC unit and CVQ nuit. The realized system shows that the transmission rates are 6-15 frames/sec according to the relative motion of the video signal.

• Journal of the Korea Society of Computer and Information
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• v.16 no.12
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• pp.131-137
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• 2011

Operating Systems is a discipline which handles complex and abstract concepts related to its components and the principles of how an operating system works. However, most of the OS courses have been textbook-oriented theoretical classes. For students who are familiar with various kinds of media, theoretical classes lead to a decline in the understanding of a lecture and difficulty concentrating. They have tried to make use of educational tools to help students understand a lecture and arouse their interests consistently. This paper describes the design and implementation of a disk scheduling simulator which shows the service processes of disk I/O requests visually. The disk scheduling simulator can be used for demonstrations of the disk scheduling algorithms. The results of the academic achievement evaluation and survey showed that a disk scheduling simulator is useful as an educational tool which causes the interests about operating systems and enhances the understanding of a lecture.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.47-52
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• 2008

The visual implementation of 3-dimensional national environment is focused by the requirement and importance in the fields such as, urban planing, telecommunication facility deployment plan, railway construction, construction engineering, spatial city development, safety and disaster prevention engineering. The currently used DEM system based on the 2-D digital maps and contour lines has limitation in implementation in reproducing the 3-D spatial city. Currently, the LiDAR data which combines the laser and GPS skill has been introduced to obtain high resolution accuracy in the altitude measurement in the advanced country. In this paper, we first introduce the LiDAR based researches in advanced foreign countries, then we propose the data generation scheme and an solution algorithm for the optimal management of our 3-D spatial u-City construction. For this purpose, LiDAR based height data transformed to DEM, and the realtime unification of the vector via digital image mapping and raster via exactness evaluation is transformed to make it possible to trace the model of generated 3-dimensional model with long distance for 3D u-city model generation.

• Journal of IKEEE
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• v.19 no.1
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• pp.10-17
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• 2015

In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.319-324
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• 2018

In this paper, we designed and implemented a code conversion method between ISO/IEC 10646 and the multi-byte code set. The Universal Multiple-Octet Coded Character Set(UCS) provides codes for more than 65,000 characters, huge increase over ASCII's code capacity of 128 characters. It is applicable to the representation, transmission, interchange, processing, storage, input and presentation of the written form of the language throughout the world. Therefore, it is so important to guide on code conversion methods to their customers during customer systems are migrated to the environment which the UCS code system is used and/or the current code systems, i.e., ASCII PC code and EBCDIC host code, are used with the UCS together. Code conversion utility including the mapping table between the UCS and IBM new host code is shown for the purpose of the explanation of code conversion algorithm and its implementation in the system. The programs are successfully executed in the real system environments and so can be delivered to the customer during its migration stage from the UCS to the current IBM code system and vice versa.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.517-525
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• 2006

In this paper, the algorithm which improve the efficiency of surveillance in spite of the change of light is proposed and confirmed by virtue of the experiments. One of the problems for the implementation of visual surveillance system is the image processing technique to overcome with the variations of illumination lights. Some conventional systems are generally not considered the error due to the change of lights because the system use at indoor. In practical, the factors of bad image can be classified to the ghosts due to the reflection of lights and shadows in a scene. Especially weak images and noises at night are decreased the performance of visual surveillance system. In the paper, the filter which improve the images with some change of illumination lights is designed and the gabor filter is used for recognition and tracking of the moving objects. In the results, the system showed that the recognition and tracking were obtained $92\sim100%$ of recognition rate at daytime, but $80\sim90%$ of nighttime.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

• Journal of The Korean Association of Information Education
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• v.19 no.4
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• pp.441-448
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• 2015

This paper describes about a software implementation for class analysis and quantization based on our video synchronization method. We proposed a new indexing method, synchronization strategies, and data structure for our analyzer implementation. We implemented a class video analyzer using intelligent multimedia technologies which can play class video selectively. Our proposed method analyzes class videos depending on the time schedule composed of introduction, development and summary stages. We apply our analysis filters to the class videos in the predefined regular intervals. We experimented on the synchronization performance of our proposed method and software. In the experimental, we could demonstrate the effectiveness and practicality of our class analyzing method within the margin of error.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.