• Title/Summary/Keyword: implementation algorithm

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Hardware Implementation of Genetic Algorithm Processor for EHW (EHW를 위한 Genetic Algorithm Processor 구현)

  • Kim, Jin-Jung;Kim, Yong-Hun;Choi, Yun-Ho;Chung, Duck-Jin
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.2827-2829
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    • 1999
  • Genetic algorithms were described as a method of solving large-scaled optimization problems with complex constraints. It has overcome their slowness, a major drawback of genetic algorithms using hardware implementation of genetic algorithm processor (GAP). In this study, we proposed GAP effectively connecting the goodness of survival-based GA, steady-state GA, tournament selection. Using Pipeline Parallel processing, handshaking protocol effectively, the proposed GAP exhibits 50% speed-up over survival-based GA which runs one million crossovers per second(1MHz). It will be used for high speed processing such of central processor of EHW, robot control and many optimization problem.

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Implementation of the adaptive ANC system improving robustness (강인성을 개선한 적응능동소음제어 시스템 구현)

  • Shin, Seung-Sik;Lee, Cheol-Ki;Oh, Hak-Jun;Koo, Choon-Keun;Chung, Chan-Soo
    • Proceedings of the KIEE Conference
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    • 1996.11a
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    • pp.55-57
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    • 1996
  • This paper presents an implementation of the adaptive ANC (Active Noise Control) system improving robustness. The system using the proposed algorithm shows a good performance of control, when the adaptive filter well does not work. We construct a real duct system and use DSP chip for experiment. Experimental results of the proposed algorithm prove the system to be superior than the conventional filtered-x LMS algorithm when the adaptive filter is out of order.

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A Study on the Implementation of Digital Protective Relay Algorithm using VHDL (VHDL을 이용한 디지털 계전 알고리즘 구현에 관한 연구)

  • Kwon O. S.;Heo J. Y.;Kim C. H.
    • Proceedings of the KIEE Conference
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    • summer
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    • pp.251-253
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    • 2004
  • Nowadays, power customer has increased and new power plants have been constructed for market demands. However, increasement of power plants make power system more complex and unstable. For this reason, the stability problem is one of the most important issues in power systems. In this paper, a study on implementation of out-of-step detection algorithm is performed. The structure of digital relay is analyzed for development of out-of-step detection algorithm. DFT block which is used to extract basic frequency of voltage is analyzed to design VHDL.

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Design and Implementation of a Genetic Algorithm for Optimal Placement (최적 배치를 위한 유전자 알고리즘의 설계와 구현)

  • 송호정;이범근
    • Journal of the Korea Society of Computer and Information
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    • v.7 no.3
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    • pp.42-48
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    • 2002
  • Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

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Implementation of the Panoramic System Using Feature-Based Image Stitching (특징점 기반 이미지 스티칭을 이용한 파노라마 시스템 구현)

  • Choi, Jaehak;Lee, Yonghwan;Kim, Youngseop
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.2
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    • pp.61-65
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    • 2017
  • Recently, the interest and research on 360 camera and 360 image production are expanding. In this paper, we describe the feature extraction algorithm, alignment and image blending that make up the feature-based stitching system. And it deals with the theory of representative algorithm at each stage. In addition, the feature-based stitching system was implemented using OPENCV library. As a result of the implementation, the brightness of the two images is different, and it feels a sense of heterogeneity in the resulting image. We will study the proper preprocessing to adjust the brightness value to improve the accuracy and seamlessness of the feature-based stitching system.

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Experimental Study of Synchronization Ratio Based on Location Update Interval in Wireless Ad Hoc Networks (무선 애드 혹 네트워크에서 패킷전송주기에 따른 동기화율 성능검증)

  • Jung, SangWoo;Han, Sanghyuck;Kim, Ki-Il
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.3
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    • pp.113-121
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    • 2019
  • Algorithms for geographical routing and location update attract the researchers' interests in wireless ad hoc networks. Even though many various schemes have been proposed, most of them cause scalability problem in small groups of nodes. To defeat this problem, flooding algorithm is widely utilized due to low complexity. However, there is no previous research work to evaluate flooding algorithm through implementation instead of simulation. In this paper, we present implementation of flooding algorithm on Raspberry Pi and performance evaluation results.

Heterogeneous Parallel Architecture for Face Detection Enhancement

  • Albssami, Aishah;Sharaf, Sanaa
    • International Journal of Computer Science & Network Security
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    • v.22 no.2
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    • pp.193-198
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    • 2022
  • Face Detection is one of the most important aspects of image processing, it considers a time-consuming problem in real-time applications such as surveillance systems, face recognition systems, attendance system and many. At present, commodity hardware is getting more and more heterogeneity in terms of architectures such as GPU and MIC co-processors. Utilizing those co-processors along with the existing traditional CPUs gives the algorithm a better chance to make use of both architectures to achieve faster implementations. This paper presents a hybrid implementation of the face detection based on the local binary pattern (LBP) algorithm that is deployed on both traditional CPU and MIC co-processor to enhance the speed of the LBP algorithm. The experimental results show that the proposed implementation achieved improvement in speed by 3X when compared to a single architecture individually.

A 4K-Capable Hardware Accelerator of Haze Removal Algorithm using Haze-relevant Features

  • Lee, Seungmin;Kang, Bongsoon
    • Journal of information and communication convergence engineering
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    • v.20 no.3
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    • pp.212-218
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    • 2022
  • The performance of vision-based intelligent systems, such as self-driving cars and unmanned aerial vehicles, is subject to weather conditions, notably the frequently encountered haze or fog. As a result, studies on haze removal have garnered increasing interest from academia and industry. This paper hereby presents a 4K-capable hardware implementation of an efficient haze removal algorithm with the following two improvements. First, the depth-dependent haze distribution is predicted using a linear model of four haze-relevant features, where the model parameters are obtained through maximum likelihood estimates. Second, the approximated quad-decomposition method is adopted to estimate the atmospheric light. Extensive experimental results then follow to verify the efficacy of the proposed algorithm against well-known benchmark methods. For real-time processing, this paper also presents a pipelined architecture comprised of customized macros, such as split multipliers, parallel dividers, and serial dividers. The implementation results demonstrated that the proposed hardware design can handle DCI 4K videos at 30.8 frames per second.

A Public Key knapsack Crytosystem Algorithm for Security in Computer Communication (컴퓨터 통신의 안전을 위한 공개키 배낭 암호계 앨고리듬)

  • 이영노;신인철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.9
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    • pp.893-900
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    • 1991
  • And this system is compared with past knapsack system by implementation of low density attack in Brickell and Lagarias, Odlyzko’s method. Also the VLSI architecture for parallel implementation of this linearly shift knapsack system is presented

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White-Box AES Implementation Revisited

  • Baek, Chung Hun;Cheon, Jung Hee;Hong, Hyunsook
    • Journal of Communications and Networks
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    • v.18 no.3
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    • pp.273-287
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    • 2016
  • White-box cryptography presented by Chow et al. is an obfuscation technique for protecting secret keys in software implementations even if an adversary has full access to the implementation of the encryption algorithm and full control over its execution platforms. Despite its practical importance, progress has not been substantial. In fact, it is repeated that as a proposal for a white-box implementation is reported, an attack of lower complexity is soon announced. This is mainly because most cryptanalytic methods target specific implementations, and there is no general attack tool for white-box cryptography. In this paper, we present an analytic toolbox on white-box implementations of the Chow et al.'s style using lookup tables. According to our toolbox, for a substitution-linear transformation cipher on n bits with S-boxes on m bits, the complexity for recovering the $$O\((3n/max(m_Q,m))2^{3max(m_Q,m)}+2min\{(n/m)L^{m+3}2^{2m},\;(n/m)L^32^{3m}+n{\log}L{\cdot}2^{L/2}\}\)$$, where $m_Q$ is the input size of nonlinear encodings,$m_A$ is the minimized block size of linear encodings, and $L=lcm(m_A,m_Q)$. As a result, a white-box implementation in the Chow et al.'s framework has complexity at most $O\(min\{(2^{2m}/m)n^{m+4},\;n{\log}n{\cdot}2^{n/2}\}\)$ which is much less than $2^n$. To overcome this, we introduce an idea that obfuscates two advanced encryption standard (AES)-128 ciphers at once with input/output encoding on 256 bits. To reduce storage, we use a sparse unsplit input encoding. As a result, our white-box AES implementation has up to 110-bit security against our toolbox, close to that of the original cipher. More generally, we may consider a white-box implementation of the t parallel encryption of AES to increase security.