• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.264-267
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• 2002

This paper proposed a effective priority selection algorithm named weighted round-robin algorithm and show the implementation result of DMAC priority selection module using prosed weighted round-robin algorithm. I parameterize timing constraints of each functional module, which decide the effectiveness of system. Proposed weighted round-robin algorithm decide the most effective module for data transmission using parameterize timing constraints and update timing parameter of each module for next transmission module selection. I implement DMAC priority selection module using this weighted round-robin algorithm and can improve the timing effective for data transmission from memory to functional module or one functional module to another functional module.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• The Journal of Society for e-Business Studies
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• v.5 no.1
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• pp.55-73
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• 2000

Recently; EC(Electronic Commerce) is increasing with high speed based on the expansion of Internet. EC which is done on the cyber space through Internet has strong point like independence from time and space. On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet. Therefore, we need the solutions that protect the security problem for safe and useful EC activity. One of these solutions is the implementation of strong cipher algorithm. NC(Nonpolynomial Complete) cipher algorithm proposed in this paper is good for the security and it overcome the limit of current 64bits cipher algorithm using 128bits key length for input, output and encryption key, Moreover, it is designed for the increase of calculation complexity and probability calculation by adapting more complex design for subkey generation regarded as one of important element effected to encryption. The result of simulation by the comparison with other cipher algorithm for capacity evaluation of proposed NC cipher algorithm is that the speed of encryption and decryption is 7.63 Mbps per block and the speed of subkey generation is 2,42 μ sec per block. So, prosed NC cipher algorithm is regarded as proper level for encryption. Furthermore, speed of subkey generation shows that NC cipher algorithm has the probability used to MAC(Message Authentication Code) and block implementation of Hash function.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.144-154
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• 1996

Proposed numerous algorithms for the policing function have mainly focused on their performances. Besides their performance evaluation, however, the VLSI-implementation of these algorithms is worth consideration as well. Although, no algorithms for the policing function have been standardized up to now, ITU-T I.371 suggests two examples of algorithms, the Virtual Scheduling Algorithm (VSA) and the Continuous State Leaky Bucket algorithm. In this paper, we suggest the architecture of a policing device implementing the VSA among various algorithms for the peak cell rate policing and discuss some issues on the implementation. We also present how to select the policing modes of the two devices used to realize various policing schemes and show the experimental results obtained under four different peak cell rate values to confirm that the device performs the policing function satisfactorily. We exploit the priority encoder to run the algorithm in parallel instead of sequentially, which reduces the operation time to a great extent.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2192-2195
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• 2003

This parer proposes a power-line phase measurement algorithm which is based on the recursive implementation of sliding-DFT. Usage of the single DFT coefficient in the conventional sliding-DFT based power-line phase measurement brings a significant error propagation when implemented in hardware with finite word-length arithmetic operations. The proposed algorithm utilizes all the N-point DFT coefficients in the recursion. Performance degradation caused by the finite word- length implementation of the algorithm is analyzed and verified with computer simulations. The robustness of the proposed phase measurement algorithm against the erroneous implementation is also confirmed by the performance analysis and simulation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.191-193
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• 2005

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.852-855
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• 2003

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.

• The Journal of Natural Sciences
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• v.7
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• pp.27-35
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• 1995

This paper introduces a VLSI (Very Large Scale Integrated Circuit) implementation of the 2-D Discrete Cosine Transform (DCT) with an application to image and video coding. This implementation, which is based upon a state space model, uses both algorithm and data partitioning to achieve high efficiency. With this implementation, the amount of data transfers between the processing elements (PEs) are reduced and all the data transfers are limitted to be local. This system accepts the input as a progressively scanned data stream which reduces the hardware required for the input data control module. With proper ordering of computations, a matrix transposition between two matrix by matrix multiplications, which is required in many 2-D DCT systems based upon a row-column decomposition, can be also removed. The new implementation scheme makes it feasible to implement a single 2-D DCT VLSI chip which can be easily expanded for a larger 2-D DCT by cascading these chips.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.29-36
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• 2009

In this paper, we proposed auto exposure(AE) algorithm and hardware implementation for apply to mobile phone camera. AE is a function that control camera exposure automatically for appropriate to object. Existing AE is using micro controller unit and there are some problems about high expense and slow processing speed. For improve these problems, we proposed AE algorithm for hardware implementation without micro controller unit therefor we can expect improvement about the content of a production and operation speed. We proposed the algorithm that is considered efficiency of hardware resource and the results of hardware implementation of proposed AE algorithm apply to mobile phone camera sensor, we verified proposed AE function.