• Journal of Korea Society of Industrial Information Systems
• /
• v.7 no.2
• /
• pp.74-81
• /
• 2002

In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.9C
• /
• pp.1337-1344
• /
• 2004

This paper deals with analysis and real-time Implementation of a wide band adaptive multirate speech codec (AMR-WB) using a fixed-point DSP of TI's TMS320C6201. In the AMR-WB codec, input speech is divided into two frequency bands, lower and upper bands, and processed independently. The lower band signal is encoded based on the ACELP algorithm and the upper band signal is processed using the random excitation with a linear prediction synthesis filter. The implemented AMR-WB system used 218 kbytes of program memory and 92 kbytes of data memory. And its proper operation was confirmed by comparing a decoded speech signal sample-by-sample with that of PC-based simulation. Maximum required time of 5 75 ms for processing a frame of 20 ms of speech validates real-time operation of the Implemented system.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.2
• /
• pp.193-199
• /
• 2008

In this paper, it is proposed the implementation of face authentication system based on real-time image processing. We described the process implementing the two steps for real-time face authentication system. At first face detection steps, we describe the face detection by using feature of wavelet transform, LoG operator and hausdorff distance matching. In the second step we describe the new dual-line principal component analysis(PCA) for real-time face recognition. It is combines horizontal line to vertical line so as to accept local changes of PCA. The proposed system is affected a little by the video size and resolution. And then simulation results confirm the effectiveness of out system and demonstrate its superiority to other conventional algorithm. Finally, the possibility of performance evaluation and real-time processing was confirmed through the implementation of face authentication system.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.10
• /
• pp.19-26
• /
• 1998

In this paper, we studied the design and implementation of fading compensation systems at aspects of narrowband mobile communication using TTIB SSB. The mobile radio channel with multipath fading places fundamental limitations on the performance of wireless communication systems. The multipath fading is compensated using pilot tone in TTIB SSB. The TTIB transceiver was implemented using the prevailing digital signal processing (DSP) techniques and compensation for the multipath fading was incorporated in the receiver in the form of DSP algorithm. In order to evaluate fading compensation performance in TTIB transceiver, we first used computer simulation. In the simulation results, we found that the TTIB transceiver could compensate for the multipath fading as expected. Second, we carried out some experiments on TTIB transceiver implementation with DSP boards and later with hardwares including RF circuits with center frequency of 145MHz. Through these experiments, we found that fading compensation performance in TTIB transceiver was almost as good as that obtained from simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.1
• /
• pp.109-116
• /
• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.4
• /
• pp.1867-1875
• /
• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of the Architectural Institute of Korea Planning & Design
• /
• v.35 no.11
• /
• pp.69-78
• /
• 2019

The purpose of this study is to propose a modeling methodology through the exchange of coordinate data of a three-dimensional custom curtain wall panel between Rhino and Revit, and to examine the validity of the model implemented in the drawing. Although the modeling means and method are different, a fundamental principle is that all three-dimensional modeling begins by defining the position of the points, the most primitive element of geometry, in the XYZ coordinate space. For the BIM modeling methodology proposal based on this geometry basic concept, the functions and characteristics associated with the points of Rhino and Revit programs are identified, and then BIM implementation process model is organized and systemized through the setting of the interoperability process algorithm. The BIM implementation process model proposed in this study is (1) Modeling and panelizing surface into individual panels using Rhino and Grasshopper; (2) Extraction of vertex coordinate data from individual panels and create CSV file; (3) Curtain wall modeling through Adaptive Component Family in Revit and (4) Automatic creation of Revit curtain wall panels through API. The proposed process model is expected to help reduce design errors and improve component and construction quality by automatically converting general elements into architectural meaningful information, automating a set of processes that build them into BIM data, and enabling consistent and integrated design management.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.22 no.3
• /
• pp.495-504
• /
• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.21 no.2
• /
• pp.131-138
• /
• 2011

The previous FPGA cluster systems for a brute force search of DES keyspace have showed cost efficient performance, but the research on optimized implementation of the DES algorithm on a single FPGA has been insufficient. In this paper, the optimized DES implementation for a single FPGA of the commercial FPGA cluster system with 77 Xilinx Virtex5-LX50 FPGAs is proposed. Design space exploration using the number of pipeline stages in a DES core, the number of DES cores and the maximum clock frequency of a DES core is performed which leads to integrating 16 DES cores running at 333MHz. Also low power design is applied to reduce the loss of performance caused by limitation of power supply on each FPGA which results in fitting 8 DES cores running at 333MHz. When the proposed DES implementations would be used in the FPGA cluster system, it is estimated that the DES key would be found at most 2.03 days and 4.06 days respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.11
• /
• pp.1377-1383
• /
• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.