• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.151-154
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• 2008

For expression of isogram in mobile GIS environments, the client needs to receive the value data with the topographical map from a server. At this point, a client can't get the entire raw data because of the mobile characteristics. The approach to get representative points and to make isogram by interpolation methods, has some problems. The approach requires huge computing overhead at the client and doesn't guarantee the correctness of the isogram. In this paper, a data structure, algorithm and implementation results for efficient transmission of contour information to a client which is constructed from a elevation information at a server, are proposed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.219-222
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• 2013

The Side Channel attack methods proposed by P.Kocher are mainly used for cryptanalysis different cipher algorithms even though they are claimed to be strongly secured. Those kinds of attacks depend on environment implementation especially on the hardware implementation of the algorithm to the crypto module. side-channel attacks are a type of attack introduced by P.Kocher and is applicable according to each environment or method that is designed. This kind of attack can analyze and also extract important information by reading the binary code data via measurement of changes in electricity(voltage) consumption, running time, error output and sounds. Thus, in this paper, we discuss recent SPA and DPA attacks as well as recent countermeasure techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.123-132
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• 2014

In this paper, an IEEE1588 based clock synchronization technique for CAN (Controller Area Network) is presented. Clock synchronization plays a key role to the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipsets has been widely adopted for the synchronization of various industrial applications using Ethernet. However, there is no chipset available for CAN. This paper presents the implementation of IEEE1588 for CAN, which is implemented using only software and CAN packets without any dedicated chipset. The proposed approach is verified by the comparison between the estimated synchronization precision with a simple model and the measured precision with experimental setup.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.30 no.6_2
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• pp.623-629
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• 2012

During the construction of crossing engineering one of the important measures to ensure the safety of subway operation is the implementation of deformation surveying to the existing subway tunnel. Guangzhou new subway line 2 engineering which crosses the existing tunnel is taken as the background. How to achieve intelligent and automatic deformation surveying forecast during the subway tunnel construction process is studied. Because large amount of surveying data exists in the subway construction, deformation analysis is difficult and prediction has low accuracy, a subway intelligent deformation prediction model based on the PBIL and support vector machine is proposed. The PBIL algorithm is used to optimize the exact key parameters combination of support vector machine though probability analysis and thereby the predictive ability of the model deformation is greatly improved. Through applications on the Guangzhou subway across deformation surveying deformation engineering the prediction method's predictive ability has high accuracy and the method has high practicality. It can support effective solution to the implementation of the comprehensive and accurate surveying and early warning under subway operation conditions with the environmental interference and complex deformation.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2064-2071
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• 2012

The generalization trend of smart phones have brought many smartphone games into daily lives. These games are mainly dependent on the interactions on the display of the phone using finger touches. On the other hand, functions for detecting the positions and actions of the phones such as gyro-sensors have been rapidly developed over the former orientation sensors and acceleration sensors. Though it has become technologically possible to detect the users' motion via the smartphone devices and to use the phone device directly as the game device, it is hard to find the actualized cases. This paper proposes a new paradigm including basic frameworks and algorithm for the games combining the motion recognitions and mutual communications on the smartphones and finally presents the details of its implementation and results.

• Journal of the Korean Society of Industry Convergence
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• v.18 no.4
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• pp.250-258
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• 2015

In this research, we proposed a new approach to implement the real-time motion control of biped robot based on voice command for unmanned FA. Voice is one of convenient methods to communicate between human and robots. To command a lot of robot task by voice, voice of the same number have to be able to be recognition voice is, the higher the time of recognition is. In this paper, a practical voice recognition system which can recognition a lot of task commands is proposed. The proposed system consists of a general purpose microprocessor and a useful voice recognition processor which can recognize a limited number of voice patterns. Given biped robots, each robot task is, classified and organized such that the number of robot tasks under each directory is net more than the maximum recognition number of the voice recognition processor so that robot tasks under each directory can be distinguished by the voice recognition command. By simulation and experiment, it was illustrated the reliability of voice recognition rates for application of the manufacturing process.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• KIEE International Transactions on Power Engineering
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• v.4A no.3
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• pp.129-133
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• 2004

This paper deals with the design and implementation of a TCSC (Thyristor Controlled Series Capacitor) simulator, which is a module for an analog type power system simulator. Principally, it presents configuration of controller hardware/software and its experimental results. An analog type power system simulator consists of numerous power system components, such as various types of generator models, scale-downed transmission line modules, transformer models, switches and FACTS (Flexible AC Transmission System) devices. It has been utilized for the verification of the control algorithm and the study of system characteristics analysis. This TCSC simulator is designed for 50% line compensation rate and considered for damping resister characteristic analysis. Its power rate is three phase 380V 20kVA. For hardware extendibility, its controller is designed with VMEBUS and its main CPU is TMS320C32 DSP (Digital Signal Processor). For real time control and communications, its controller is applied to the RTOS (Real Time Operation System) for multi-tasking. This RTOS is uC/OS-II. The experimental results of capacitive mode and inductive mode operations verify the fundamental operations of the TCSC.